Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.
Quantum control processors (QCPs) bridge the gap between the quantum software and the hardware backend to construct full-stack quantum computers. In this study, the quantum backend interface is responsible for generating pulses to control qubits, where commercial waveform generators or specific converters are typically needed. A radio frequency system-on-chip (RFSoC)-based QCP supports a direct control pulse synthesis without additional components. Therefore, in this work, we propose an RFSoC-based QCP that integrates the processor and pulse generation logic onto a single board. With the help of the proposed instruction set and efficient microarchitecture implementation, the QCP offers large scalability for controllable qubits, while supporting different physical platforms.
Advanced quantum physics experiments place strict demands on control electronics, including phase-coherent multichannel RF/microwave generation, precise timing synchronization, low-latency response, and simultaneous support for wideband and near-DC signal processing. Existing control platforms often face trade-offs between channel count, integration level, and real-time performance, limiting scalability and experimental flexibility. In this work, we present a highly integrated real-time control system based on an XCZU49DR RFSoC. The platform integrates up to 16 RF DAC channels (9.85 GSa/s) and 16 RF ADC channels (2.5GSa/s) on a single chip, enabling synchronous multichannel signal generation and acquisition with deterministic timing. A custom RF front-end supports both broadband RF operation and low-frequency signal conditioning, while on-chip digital up/down conversion and programmable logic enable flexible waveform synthesis and real-time data processing. Performance characterization shows clean RF and microwave generation with spurious components suppressed below −59.0dBm at 200MHz and below −62.6dBm at 2.9GHz, while phase noise reaches −120.0dBc/Hz and −96.9dBc/Hz at 1kHz offset for 200MHz and 2.9GHz carriers, respectively, confirming low-noise and phase-coherent operation over a wide frequency range. The proposed platform provides a compact, scalable, and reconfigurable solution for quantum control and precision measurement. It is currently being applied to experiments involving NV centers and trapped ions, and can be readily adapted to other quantum systems, offering a practical foundation for next-generation
Signal generators for qubit control and measure-ments play a key role in quantum computers in terms of latency and scalability. Typically, the control pulses are generated by arbitrary waveform generators (AWGs) via preloaded lookup tables. However, this method lacks the flexibility to adjust phase and frequency in complicated programs, such as variational quantum eigensolvers (VAE) or pulse shape optimization al-gorithms. Therefore, we propose a quantum control system composed of a quantum control processor (QCP) and a run-time waveform-configurable signal generator in this work. For the signal generator, we developed a parallelized direct digital synthesis (DDS) structure to adaptively generate waveforms without requiring the entire waveform to be preloaded. The QCP, based on HiSEP-Q, is optimized with a deeper pipelined architecture to increase frequency and match the high bandwidth of signal generators. Additionally, we introduce a synchronization architecture in the QCP to manage uneven delays among different generation threads. Validated on the ZCU216 platform, our system achieves flexible signal generation with an average latency of 20 ns and reduces memory usage by more than 50%.
Quantum computing promises an effective way to solve targeted problems that are classically intractable. Among them, quantum computers built with superconducting qubits are considered one of the most advanced technologies, but they suffer from short coherence times. This can get exaggerated when they are controlled directly by general-purpose host machines, which in turn leads to the loss of quantum information. To mitigate this, we need quantum control processors (QCPs) positioned between quantum processing units (QPUs) and host machines to reduce latencies. However, existing QCPs are built on top of designs with no or inefficient scalability, requiring a large number of instructions when scaling to more qubits. In addition, interactions between current QCPs and host machines require frequent data transmissions and offline computations to obtain final results from hundreds of repeated executions, which limits the performance of quantum computers.In this paper, we propose a QCP — called HiSEP-Q — featuring a novel quantum instruction set architecture (QISA) and its microarchitecture implementation. For efficient control, we utilize mixed-type addressing modes and mixed-length instructions in HiSEP-Q, which provides an efficient way to concurrently address more than 100 qubits. Further, for efficient read-out and analysis, we develop a novel onboard accumulation and sorting unit, which eliminates the data transmission of raw data between the QCPs and host machines and enables real-time result processing. Compared to the state-of-the-art, our proposed QISA achieves at least 62% and 28% improvements in encoding efficiency with real and synthetic quantum circuits, respectively. We also validate the microarchitecture on a field-programmable gate array (FPGA), which exhibits low power and resource consumption, even as the number of qubits scales to 100. Both hardware and ISA evaluations demonstrate that HiSEP-Q features high scalability and efficiency toward the number of controlled qubits.
Execution of quantum algorithms requires a quantum computer architecture with a dedicated quantum instruction set that is capable of supporting translation of workloads into actual quantum operations acting on the qubits. State-of-the-art qubit control setups typically utilize general purpose test instruments such as arbitrary waveform generators (AWGs) to generate a limited set of waveforms or pulses. These waveforms are precomputed and stored prior to execution, and then used to produce control pulses during execution. Besides their prohibitive cost and limited scalability, such instruments suffer from poor programmability due to the absence of an instruction set architecture (ISA). Limited memory for pulse storage ultimately determines the total number of supported quantum operations. In this work, we present a scalable qubit control system that enables efficient qubit control using a flexible ISA to drive a direct digital synthesis (DDS) pipeline producing nanosecond-accurate qubit control signals dynamically. The designed qubit controller provides a higher density of control channels, a scalable design, better programmability, and lower cost compared to state-of-the-art systems. In this work, we discuss the new qubit controller's capabilities, its architecture and instruction set, and present experimental results for coherent qubit control.
Arbitrary Waveform Generators (AWGs) have widespread applications in telecommunications, quantum computing, and biomedical engineering, among others, due to their ability to generate a wide range of waveforms precisely and instantaneously. This work focuses on developing a scalable and energy-efficient AWG for qubit control. A simple methodology for bringing up a Radio-Frequency System-on-Chip (RFSoC) board and using it to generate various arbitrary waveforms has been discussed. A software-hardware codesign paradigm has been used in this work to dynamically control the output frequency, voltage and shape of the arbitrary waveforms. Similarly, the on-the-fly programmability of four Digital to Analog convertor (DAC) channels and four Analog to Digital Converter (ADC) channels have been tested. The voltage and frequency response of the DAC output has also been characterised to better understand the limitations of the RFSoC. The DAC-ADC loopback characterisation was also performed to prepare the RFSoC for qubit state readout measurements. Over the last few decades, the Direct Digital Synthesiser (DDS) has been a popular choice for generating specific waveforms, such as sinusoidal and ramp waveforms, due to its low cost, simple design, and high precision. Several prior-art works were surveyed, and the trade-offs and strengths of each architecture were summarised. A benchmarking table is prepared based on the Power, Performance and Area (PPA) analysis to make design selection easier for DDS designers. Two Figure of Merit definitions and scaling equations have also been used to normalise the specifications to a target process node (28 nm CMOS), to provide a more accurate comparison among state-of-the-art DDS designs on Application Specific Integrated Circuits (ASICs), and to set expectations for future architectural advancements in DDS design. Finally, a viable DDS-based AWG architecture for ASIC implementation has also been proposed based on the benchmarking.
We introduce a Xilinx RF System-on-Chip (RFSoC)-based qubit controller (called the Quantum Instrumentation Control Kit, or QICK for short), which supports the direct synthesis of control pulses with carrier frequencies of up to 6 GHz. The QICK can control multiple qubits or other quantum devices. The QICK consists of a digital board hosting an RFSoC field-programmable gate array, custom firmware, and software and an optional companion custom-designed analog front-end board. We characterize the analog performance of the system as well as its digital latency, important for quantum error correction and feedback protocols. We benchmark the controller by performing standard characterizations of a transmon qubit. We achieve an average gate fidelity of Favg=99.93%. All of the schematics, firmware, and software are open-source.