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IEEE Transactions on Circuits & Systems II Express Briefs

A Cryogenic 12 GHz Frequency Doubler With Temperature Compensation for Trapped-Ion Quantum Computer

Peter Toth, Alexander Meyer, S. Halama, Hiroki Ishikuro, Вадим Іссаков

Published Jun 28, 2023• 4 citations
Publisher

Abstract

This brief presents a frequency doubler (FD) for a microwave-control system intended for an$^{171}\text {Yb}^{+}$ion-trap-based quantum computer. The circuit is optimized for frequency multiplication from 11GHz to 13 GHz with a ≥29 dBc fundamental- and third harmonic rejection over the entire frequency range and peak HRR1/HRR3 of 37 dBc/ 39 dBc. This enables the microwave frequency generation to drive the hyperfine transitions in the electronic ground state of an$^{171}\text {Yb}^{+}$ion at 12.6 GHz. Cryogenic measurements of the FD down to 4.5 K enable circuit functionality verification for the intended low-temperature operation. Additionally, insights into the cryogenic temperature effects of the employed BiCMOS technology are obtained and used to derive a biasing control methodology for constant performance in the temperature range of 300K to 4.5K. The proposed circuit is silicon-proven and fabricated in a$\mathrm {0.13~ \mu \text {m} }$SiGe BiCMOS process, consuming a core area of only 0.034 mm2.

DOI
10.1109/tcsii.2023.3290260

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This brief presents a frequency doubler (FD) for a microwave-control system intended for an171Yb+^{171}\text {Yb}^{+}171Yb+ion-trap-based quantum computer. The circuit is optimized for frequency multiplication from 11GHz to 13 GHz with a ≥29 dBc fundamental- and third harmonic rejection over the entire frequency range and peak HRR1/HRR3 of 37 dBc/ 39 dBc. This enables the microwave frequency generation to drive the hyperfine transitions in the electronic ground state of an171Yb+^{171}\text {Yb}^{+}171Yb+ion at 12.6 GHz. Cryogenic measurements of the FD down to 4.5 K enable circuit functionality verification for the intended low-temperature operation. Additionally, insights into the cryogenic temperature effects of the employed BiCMOS technology are obtained and used to derive a biasing control methodology for constant performance in the temperature range of 300K to 4.5K. The proposed circuit is silicon-proven and fabricated in a0.13 μm\mathrm {0.13~ \mu \text {m} }0.13 μmSiGe BiCMOS process, consuming a core area of only 0.034 mm2.
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This work presents a power amplifier (PA) for microwave-driven entanglement operation in ion-trap-based Ytterbium qubit gates. The design is optimized for a center frequency of 13 GHz with a 3 dB bandwidth of 6 GHz thereby fulfilling the requirements to drive the 12.6 GHz hyperfine transisiton in the electronic ground state of a171Yb+ion. The PA achieves a saturated output power of 14 dBm and a gain of 20 dB at the center frequency. Due to a tunable operating point it is possible to realize a power-efficient amplitude modulation allowing for a qubit-gate fidelity improvement. The presented circuit achieves a measured power-added-efficiency (PAE) of 28 %. Due to maintaining an electrically stable operation during operation-point changes, this circuit is highly suitable for analyzing the effect of various pulse envelopes on the gate fidelity. The proposed circuit is silicon-proven and fabricated in a 0.13 µm SiGe BiCMOS process covering a core area of only 0.14 mm2.
Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10–6range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10–4[3], [4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5], [6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
This thesis proposes a pathway to realizing large-scale quantum computing integrated circuits based on the monolithic integration of high-temperature (1–4 K) semiconductor qubits with their associated control and readout circuitry. High-frequency device characterization was performed on production 22-nm FDSOI technology at room and cryogenic temperatures (down to 3.3 K) to inform a cryogenic circuit design methodology in the absence of low-temperature device models. The methodology was demonstrated with a TIA qubit-readout chain that was, for the first time, monolithically integrated with electron and hole quantum dot structures. The prospects of FDSOI SiGe BiCMOS technology would enable similar integration with higher performance HBT devices. As a first step, design of a 240-GHz direct conversion I-Q receiver is showcased in 55-nm SiGe BiCMOS, intended for frequency-division multiplexed readout of many qubits. The measured IF-bandwidth of 59 GHz makes it suitable for high data-rate communication and large-scale quantum processors.