Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10–6range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10–4[3], [4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5], [6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
Trapped ions (TI) are one of the leading platforms for the realization of a universal quantum computer (QC). They feature several advantages compared to competing technologies. Key benefits of TI qubits utilizing hyperfine transitions are the long achievable coherence time T2 of up to hours and the almost infinite excited state lifetime T1 [1]. The error rate of single-qubit operations is already in the 10–6range [2], while the error rate of entangled two-qubit gates approaches the fault tolerance error-correction threshold of 10–4[3], [4]. The combined state preparation and measurement fidelity depends on the ion species and is usually above 99.5%. Ion traps can comfortably work at moderate cryogenic temperatures around 4 K, and even room temperature (RT) operation has been demonstrated [4]. The quantum-charge-coupled-device (QCCD) [5], [6] architecture allows scalable ion trapping and shuttling, thus enabling all-to-all qubit interconnection.
This article presents a cryo-BiCMOS system on chip (SoC) designed for single and two-qubit gate operations for quantum computers (QCs) based on beryllium trapped-ions (TIs). Signal generation from 0.7 to 1.6 GHz is supported, covering all microwave transitions in a9Be+QC realization. An integrated 48-kbit waveform memory is implemented for improved two-qubit gate fidelity. The fabricated IC is verified in a 4 K environment with up to 4 qubits, thus enabling quantum processor unit (QPU) cointegration. IC operation up to RT ensures compatibility with future system realizations. Measurements demonstrate qubit state control with an oscillation amplitude of 94% before SPAM correction and Rabi oscillation rate of 172 kHz. Evaluations of long sequences ofσxgates indicate control of the quantum state with high quality. Interaction with one computational zone is possible at a total power consumption of 86 mW translating to 21.5 mW/qubit in the presented measurements. Comparison with the state-of-the-art controller reveals drastic power and form-factor reduction at comparable performance, thus paving the way for a scalable TI platform. The chip is fabricated in a 0.13-μmSiGe BiCMOS technology. To the best of our knowledge, this is the first reported from-scratch system design for TI-based QC concluding with a qubit state manipulation demonstration.
The trapped-ion QCCD (quantum charge-coupled device) architecture proposal lays out a blueprint for a universal quantum computer. The design begins with electrodes patterned on a two-dimensional surface configured to trap multiple arrays of ions (or ion crystals). Communication within the ion crystal network allows for the machine to be scaled while keeping the number of ions in each crystal to a small number, thereby preserving the low error rates demonstrated in trapped-ion experiments. By proposing to communicate quantum information by moving the ions through space to interact with other distant ions, the architecture creates a quantum computer endowed with full-connectivity. However, engineering this fully-connected computer introduces a host of difficulties that have precluded the architecture from being fully realized in the twenty years since its proposal. Using a Honeywell cryogenic surface trap, we report on the integration of all necessary ingredients of the QCCD architecture into a programmable trapped-ion quantum computer. Using four and six qubit circuits, the system level performance of the processor is quantified by the fidelity of a teleported CNOT gate utilizing mid-circuit measurement and a quantum volume measurement of 26=64. By demonstrating that the low error rates achievable in small ion crystals can be successfully integrated with a scalable trap design, parallel optical delivery, and fast ion transport, the QCCD architecture is shown to be a viable path toward large quantum computers. Atomic ions provide perfectly identical, high-fidelity qubits. Our work shows that the QCCD architecture built around these qubits will provide high performance quantum computers, likely enabling important near-term demonstrations such as quantum error correction and quantum advantage.
Trapped ions are one of the leading platforms for building scalable quantum information processors. Current ion traps run on less than 100 qubits. A useful quantum computer needs to operate thousands or even millions of qubits. If systems reach gate fidelities that allow for quantum error correction, gate errors below the physical fidelity can be reached, which is important for scaling. The most promising platform for scaling up ion-based quantum computers are surface electrode traps in connection with the so-called QCCD (Quantum Charge Coupled Device) architecture. In an evolution of the standard (laser-based) approach to quantum logic gates, gates can be performed by applying an oscillating magnetic near-field gradient to the ions. Current fidelities are about one order of magnitude away from reaching the fault tolerant threshold with no fundamental limitations in sight. Scaling QCCDs is impeded by heating rates of the ions as well as vacuum quality. Ions have to be stored for at least as long as it takes for an algorithm to run and subsequent readout. Collisions with background gas and heating can expel ions from the trap. The microwave near-field approach of driving gates benefits from ions that are trapped close to the trap surface. Unfortunately, heating becomes more prominent near the surface. A cryogenic environment reduces the background pressure by several orders of magnitude and the kinetic energy of gas molecules by two orders of magnitude. Heating rates in a cryogenic trap are about two orders of magnitude lower than in a room temperature trap with otherwise equal physical properties. To operate a QCCD processor, it is required to employ phase-stable Raman laser beams. The cryogenic design of the apparatus needs to take into account the resulting requirements for ultra-low vibration amplitudes. This is particularly relevant for closed-cycle cooling systems, which are desirable from an economic point of view compared to liquid cryostats that boil off helium, but which also feature moving mechanical parts that can introduce a serious amount of vibrations. Here, we present a vibration isolated closed cycle Gifford-McMahon cryocooler with record low vibration amplitudes of 29 nm (RMS=7.8 nm) in the vertical and 51 nm (RMS=13.5 nm) in the horizontal direction. It contains a self-sustained inner vacuum chamber that houses the trap. It features 100 DC connections, 10 of which are able to carry up to 1 A of current and 8 high frequency lines. At 5 K, we can apply continuous 3.4 W of microwave power continuously at 1 GHz to the trap electrodes without heating the system. This is about 5.8 times more than state of the art near-field gates require. We also present the laser systems required to for single-shot ablation loading and Doppler cooling of Be ions: a 70 mW 313 nm Dopper cooling laser, a 1064 nm ns-pulse laser for ablation of neutral beryllium atoms and a 235 nm laser for ionizing them. The detection system features an in vacuum imaging system on a cryogenic 3D translation stage that is able to scan and image the complete surface of an ion trap. The light can be detected on a photomultiplier tube or spatially resolved on an EMCCD camera. Our trap features a meander structure for driving gates and can trap up to 5 ions of which we, so far, did not lose any due to background gas collisions. This hints at a vacuum pressure of 1e-12 mbar or lower. The demonstrated system could hold a cryogenic QCCD chip with a few 10 qubits
Abstract The trapped-ion quantum charge-coupled device (QCCD) proposal1, 2 lays out a blueprint for a universal quantum computer that uses mobile ions as qubits. Analogous to a charge-coupled device (CCD) camera, which stores and processes imaging information as movable electrical charges in coupled pixels, a QCCD computer stores quantum information in the internal state of electrically charged ions that are transported between different processing zones using dynamic electric fields. The promise of the QCCD architecture is to maintain the low error rates demonstrated in small trapped-ion experiments3–5 by limiting the quantum interactions to multiple small ion crystals, then physically splitting and rearranging the constituent ions of these crystals into new crystals, where further interactions occur. This approach leverages transport timescales that are fast relative to the coherence times of the qubits, the insensitivity of the qubit states of the ion to the electric fields used for transport, and the low crosstalk afforded by spatially separated crystals. However, engineering a machine capable of executing these operations across multiple interaction zones with low error introduces many difficulties, which have slowed progress in scaling this architecture to larger qubit numbers. Here we use a cryogenic surface trap to integrate all necessary elements of the QCCD architecture—a scalable trap design, parallel interaction zones and fast ion transport—into a programmable trapped-ion quantum computer that has a system performance consistent with the low error rates achieved in the individual ion crystals. We apply this approach to realize a teleported CNOT gate using mid-circuit measurement6, negligible crosstalk error and a quantum volume7 of 26 = 64. These results demonstrate that the QCCD architecture provides a viable path towards high-performance quantum computers.
Trapped-ion quantum computers offer high-fidelity operations, long coherence times, and all-to-all connectivity within a single trap. However, scaling to large circuits is limited by the trap's ion capacity. The QCCD architecture addresses this by enabling ion shuttling across multiple traps, but excessive shuttling increases execution time and degrades fidelity. This paper presents an improved ion-shuttling approach targeting linear QCCD architectures. Building on a state-of-the-art approach [27] for linear trapped-ion devices, our approach introduces a front-layer-based scheduling method that dynamically prioritizes executable gates, along with a novel destination trap selection method for ion-shuttling, effectively reducing unnecessary ion movements. We also present a look-ahead gate selection strategy based on the gate dependency graph, avoiding the high runtime of the gate proximity approach used in the state-of-the-art approach, especially in circuits with all-to-all communication. Our approach achieves up to a 37.67% reduction in shuttle count and up to a 74.91% reduction in compilation time compared to the state-of-the-art approach for linear trapped-ion devices on actual NISQ benchmarks and synthetic circuits. On average, our approach achieves a 16.44% reduction in shuttle count and a 30.77% reduction in compilation time across all test cases. These improvements highlight the effectiveness of our approach, particularly for actual circuits.
Trapped ions (TI) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies such as superconducting qubits, including high qubit quality, coherence and connectivity. However, current TI systems are small in size, with 5-20 qubits and typically use a single trap architecture which has fundamental scalability limitations. To progress towards the next major milestone of 50-100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50-100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology and gate implementations and the need to match diverse application resource requirements.Towards realizing QCCD-based TI systems with 50-100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology and operation implementation methods. To enable our study, we built a design toolflow which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near-future and accelerate the progress towards practical QC systems.