Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Integrated Control Addressing Circuits for a Surface Code Quantum Computer in Silicon

Rubaya Absar, Zach D. Merino, Hazem Elgabra, Xuesong Chen, Jonathan Baugh, Lan Wei

Published Dec 7, 2022• 0 citations
Publisher

Abstract

Quantum computers require a coordinated operation on a large number of quantum bits (qubits), presenting considerable obstacles such as system integration on a large scale, individual qubits control with precision, and significant error correction overhead. Silicon (Si) quantum dot (QD) spin qubits paired with CMOS control circuits promise a scalable solution due to its potential for large-scale integration utilizing well-established semiconductor technologies. This paper proposes a control addressing scheme for QD spin qubits operating on a node network architecture. Compared to the typical 2-dimensional array architecture, this approach considerably lowers the area constraint for control signal routing. Scalable circuits are designed to route the control signals for local and global operations of a surface code quantum error correction through the modular design of tiered switches controlled by demultiplexers. The proposed method is a critical step toward implementing scalable solid-state quantum processors.

DOI
10.1145/3565478.3572541

Related papers

Scalable Addressing Circuits for a Surface Code Silicon-based Quantum Computer

Rubaya Absar, Zach D. Merino, Hazem Elgabra +3 more

A scalable circuit is designed to provide control signals for local and global operation of surface quantum error correction codes through a modular design of tiered switches controlled by demultiplexers. Critical power, performance, and area (PPA) merits are reported through a TSMC 65 nm technology implementation. The proposed design is an important step toward the implementation of scalable solid-state quantum processors with integrated cryo-electronics.

•Apr 28, 2023•1 citation

Scalable Addressing Circuits for a Surface Code Silicon-based Quantum Computer

Rubaya Absar, Zach D. Merino, Hazem Elgabra +3 more

A scalable circuit is designed to provide control signals for local and global operation of surface quantum error correction codes through a modular design of tiered switches controlled by demultiplexers. Critical power, performance, and area (PPA) merits are reported through a TSMC 65 nm technology implementation. The proposed design is an important step toward the implementation of scalable solid-state quantum processors with integrated cryo-electronics.

•Apr 28, 2023•0 citations

Scalable Addressing Circuits for a Surface Code Quantum Computer in Silicon

Rubaya Absar, Hazem Elgabra, Xuesong Chen +3 more

Practical quantum computers require coordinated operation on a large number of qubits$(\sim 10^{4})$, posing significant implementation challenges. In this paper, we summarize our recent work on scalable CMOS circuits to route control signals in a silicon MOS quantum dot spin qubit. We also present a cryogenic compact model enabling circuit design and simulation at cryogenic temperatures. The proposed design is an important step toward implementation of scalable solid-state quantum processors.

IEEE Electron Devices Technology & Manufacturing Conference (EDTM)•Mar 7, 2023•0 citations

Silicon CMOS architecture for a spin-based quantum computer

Menno Veldhorst, H. G. J. Eenink, C. H. Yang +1 more

Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

arXiv:1609.09700•Nature Communications•Nov 20, 2017•397 citations

Silicon CMOS architecture for a spin-based quantum computer

Menno Veldhorst, H. G. J. Eenink, Chih Hwan Yang +1 more

Abstract Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.

•Jan 1, 2017•166 citations

Development of Control Circuits for Silicon MOS Quantum Dot Qubit Network

Rubaya Absar

Future quantum processors intend to operate on millions of qubits and Silicon Metal Oxide Semiconductor (MOS) Quantum Dot qubits are a good fit for such a large-scale system due to their compactness in size and large coherence time. To control the operations of the qubits in such a large-scale system, efficient and careful design of the control circuits is very challenging. Here, in this thesis a control circuit is designed for silicon MOS quantum dot qubits operating on a node/ network architecture. Rather than using a 2D array of quantum dots, a node/ network architecture provides enough space for the wiring of integrated control circuits. The control circuit designed here is expected to work on millikelvin (mK) temperature and number of control lines from the mK temperature to 1-4 K temperature, where the digital control systems are operated, is reduced significantly compared to the number of qubits. The reduction in number of control lines from mK temperature is one of the basic requirements while scaling up. All these control circuits operate on the quantum dots based on the assumption that, all the dots are at same potential throughout the network. In practice due to fabrication variations and connection differences the potential of quantum dots varies from qubit to qubit. To solve this problem and pre-tune all the quantum dots to same potential prior to the operation of control circuit, a device level error correcting scheme is introduced and verified by simulation in this thesis.

•Apr 23, 2021•0 citations
Quantum computers require a coordinated operation on a large number of quantum bits (qubits), presenting considerable obstacles such as system integration on a large scale, individual qubits control with precision, and significant error correction overhead. Silicon (Si) quantum dot (QD) spin qubits paired with CMOS control circuits promise a scalable solution due to its potential for large-scale integration utilizing well-established semiconductor technologies. This paper proposes a control addressing scheme for QD spin qubits operating on a node network architecture. Compared to the typical 2-dimensional array architecture, this approach considerably lowers the area constraint for control signal routing. Scalable circuits are designed to route the control signals for local and global operations of a surface code quantum error correction through the modular design of tiered switches controlled by demultiplexers. The proposed method is a critical step toward implementing scalable solid-state quantum processors.
Practical quantum computers require coordinated operation on a large number of qubits(∼104)(\sim 10^{4})(∼104), posing significant implementation challenges. In this paper, we summarize our recent work on scalable CMOS circuits to route control signals in a silicon MOS quantum dot spin qubit. We also present a cryogenic compact model enabling circuit design and simulation at cryogenic temperatures. The proposed design is an important step toward implementation of scalable solid-state quantum processors.
Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Abstract Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Future quantum processors intend to operate on millions of qubits and Silicon Metal Oxide Semiconductor (MOS) Quantum Dot qubits are a good fit for such a large-scale system due to their compactness in size and large coherence time. To control the operations of the qubits in such a large-scale system, efficient and careful design of the control circuits is very challenging. Here, in this thesis a control circuit is designed for silicon MOS quantum dot qubits operating on a node/ network architecture. Rather than using a 2D array of quantum dots, a node/ network architecture provides enough space for the wiring of integrated control circuits. The control circuit designed here is expected to work on millikelvin (mK) temperature and number of control lines from the mK temperature to 1-4 K temperature, where the digital control systems are operated, is reduced significantly compared to the number of qubits. The reduction in number of control lines from mK temperature is one of the basic requirements while scaling up. All these control circuits operate on the quantum dots based on the assumption that, all the dots are at same potential throughout the network. In practice due to fabrication variations and connection differences the potential of quantum dots varies from qubit to qubit. To solve this problem and pre-tune all the quantum dots to same potential prior to the operation of control circuit, a device level error correcting scheme is introduced and verified by simulation in this thesis.