Future quantum processors intend to operate on millions of qubits and Silicon Metal Oxide Semiconductor (MOS) Quantum Dot qubits are a good fit for such a large-scale system due to their compactness in size and large coherence time. To control the operations of the qubits in such a large-scale system, efficient and careful design of the control circuits is very challenging. Here, in this thesis a control circuit is designed for silicon MOS quantum dot qubits operating on a node/ network architecture. Rather than using a 2D array of quantum dots, a node/ network architecture provides enough space for the wiring of integrated control circuits. The control circuit designed here is expected to work on millikelvin (mK) temperature and number of control lines from the mK temperature to 1-4 K temperature, where the digital control systems are operated, is reduced significantly compared to the number of qubits. The reduction in number of control lines from mK temperature is one of the basic requirements while scaling up. All these control circuits operate on the quantum dots based on the assumption that, all the dots are at same potential throughout the network. In practice due to fabrication variations and connection differences the potential of quantum dots varies from qubit to qubit. To solve this problem and pre-tune all the quantum dots to same potential prior to the operation of control circuit, a device level error correcting scheme is introduced and verified by simulation in this thesis.
Future quantum processors intend to operate on millions of qubits and Silicon Metal Oxide Semiconductor (MOS) Quantum Dot qubits are a good fit for such a large-scale system due to their compactness in size and large coherence time. To control the operations of the qubits in such a large-scale system, efficient and careful design of the control circuits is very challenging. Here, in this thesis a control circuit is designed for silicon MOS quantum dot qubits operating on a node/ network architecture. Rather than using a 2D array of quantum dots, a node/ network architecture provides enough space for the wiring of integrated control circuits. The control circuit designed here is expected to work on millikelvin (mK) temperature and number of control lines from the mK temperature to 1-4 K temperature, where the digital control systems are operated, is reduced significantly compared to the number of qubits. The reduction in number of control lines from mK temperature is one of the basic requirements while scaling up. All these control circuits operate on the quantum dots based on the assumption that, all the dots are at same potential throughout the network. In practice due to fabrication variations and connection differences the potential of quantum dots varies from qubit to qubit. To solve this problem and pre-tune all the quantum dots to same potential prior to the operation of control circuit, a device level error correcting scheme is introduced and verified by simulation in this thesis.
Quantum computers require a coordinated operation on a large number of quantum bits (qubits), presenting considerable obstacles such as system integration on a large scale, individual qubits control with precision, and significant error correction overhead. Silicon (Si) quantum dot (QD) spin qubits paired with CMOS control circuits promise a scalable solution due to its potential for large-scale integration utilizing well-established semiconductor technologies. This paper proposes a control addressing scheme for QD spin qubits operating on a node network architecture. Compared to the typical 2-dimensional array architecture, this approach considerably lowers the area constraint for control signal routing. Scalable circuits are designed to route the control signals for local and global operations of a surface code quantum error correction through the modular design of tiered switches controlled by demultiplexers. The proposed method is a critical step toward implementing scalable solid-state quantum processors.
Practical quantum computers require coordinated operation on a large number of qubits(∼104), posing significant implementation challenges. In this paper, we summarize our recent work on scalable CMOS circuits to route control signals in a silicon MOS quantum dot spin qubit. We also present a cryogenic compact model enabling circuit design and simulation at cryogenic temperatures. The proposed design is an important step toward implementation of scalable solid-state quantum processors.
Future universal quantum computers solving problems of practical relevance are expected to require at least 106 qubits, which is a massive scale-up from the present numbers of less than 50 qubits operated together. Out of the different types of qubits, solid state qubits are considered to be viable candidates for this scale-up, but interfacing to and controlling such a large number of qubits is a complex challenge that has not been solved yet. One possibility to address this challenge is to use qubit control circuits located close to the qubits at cryogenic temperatures. In this work we evaluate the feasibility of this idea, taking as a reference the physical requirements of a two-electron spin qubit and the specifications of a standard 65 nm complementary metal-oxide-semiconductor (CMOS) process. Using principles and flows from electrical systems engineering we provide realistic estimates of the footprint and of the power consumption of a complete control-circuit architecture. Our results show that with further research it is possible to provide scalable electrical control in the vicinity of the qubit, with our concept.
Abstract The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer.
Abstract Even the quantum simulation of an apparently simple molecule such as Fe2S2requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore’s law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for fault-tolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal–oxide–semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal–oxide–semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal–oxide–semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal–oxide–semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal–oxide–semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via time-division, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm2for the 10 and 7-nm technology nodes, respectively, for the Steane code. The density is one and two orders of magnitude less for surface codes and for concatenated codes, respectively. Such values provide a benchmark for the development of fault-tolerant quantum algorithms by circuital quantum information based on silicon platforms and a guideline for other technologies in general.
Quantum computers have gained widespread interest as they can potentially solve problems that are intractable even for today’s supercomputers, such as the simulation of quantum systems as initially proposed by Feynman. To achieve such tremendous progress, a quantum computer relies on processing the information stored in quantum bits (qubits), the fundamental units of quantum computation, similar to the bits in a classical (i.e., non-quantum) processor. In general, a quantum processor comprising several qubits is connected through a quantum-to-classical interface consisting of classical electrical circuits for manipulating and reading out their quantum state. The accuracy of an operation on a qubit is characterized using the fidelity, which is 100 % in case of a perfect operation. In practice, a fidelity between 99 % and 99.9 % is typically achieved in today’s experiments with less than 100 qubits, limited by non-idealities in the control signals and by the implementation of the physical qubit itself. Since such qubit fidelities are too low to execute relevant quantum algorithms, quantum error correction schemes have been developed which rely on a much larger number of qubits to correct for possible errors, resulting in the need for quantum processors with thousands or millions of qubits. Solid-state qubits promise the largescale integration required to scale to millions of qubits, as they exploit the lithographic fabrication techniques borrowed from the semiconductor industry. However, state-of-theart solid-state qubits, such as transmons and single-electron spin qubits, must be typically cooled to cryogenic temperatures in a dilution refrigerator to exhibit quantum behavior. Because of the limited number of qubits (< 100) in state-of-theart solid-state quantum processors, the classical controller is currently implemented by general-purpose instruments or by tailor-made controllers operating at room temperature connected via several wires to the qubits in the cryogenic chamber. However, these systems must scale to support millions of qubits. While scaling up the underlying quantum processor is already exceptionally challenging, building the electronics required to interface such a large-scale processor is just as relevant and arduous.