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Scalable Addressing Circuits for a Surface Code Silicon-based Quantum Computer

Rubaya Absar, Zach D. Merino, Hazem Elgabra, Xuesong Chen, Jonathan Baugh, Lan Wei

Published Apr 28, 2023• 0 citations
Publisher

Abstract

A scalable circuit is designed to provide control signals for local and global operation of surface quantum error correction codes through a modular design of tiered switches controlled by demultiplexers. Critical power, performance, and area (PPA) merits are reported through a TSMC 65 nm technology implementation. The proposed design is an important step toward the implementation of scalable solid-state quantum processors with integrated cryo-electronics.

DOI
10.36227/techrxiv.22685098

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A scalable circuit is designed to provide control signals for local and global operation of surface quantum error correction codes through a modular design of tiered switches controlled by demultiplexers. Critical power, performance, and area (PPA) merits are reported through a TSMC 65 nm technology implementation. The proposed design is an important step toward the implementation of scalable solid-state quantum processors with integrated cryo-electronics.
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Practical quantum computers require coordinated operation on a large number of qubits(∼104)(\sim 10^{4})(∼104), posing significant implementation challenges. In this paper, we summarize our recent work on scalable CMOS circuits to route control signals in a silicon MOS quantum dot spin qubit. We also present a cryogenic compact model enabling circuit design and simulation at cryogenic temperatures. The proposed design is an important step toward implementation of scalable solid-state quantum processors.
Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
Abstract Recent advances in quantum error correction codes for fault-tolerant quantum computing and physical realizations of high-fidelity qubits in multiple platforms give promise for the construction of a quantum computer based on millions of interacting qubits. However, the classical-quantum interface remains a nascent field of exploration. Here, we propose an architecture for a silicon-based quantum computer processor based on complementary metal-oxide-semiconductor (CMOS) technology. We show how a transistor-based control circuit together with charge-storage electrodes can be used to operate a dense and scalable two-dimensional qubit system. The qubits are defined by the spin state of a single electron confined in quantum dots, coupled via exchange interactions, controlled using a microwave cavity, and measured via gate-based dispersive readout. We implement a spin qubit surface code, showing the prospects for universal quantum computation. We discuss the challenges and focus areas that need to be addressed, providing a path for large-scale quantum computing.
While the power of quantum computers scales exponentially with the number of qubits, harnessing this power is challenging, due to complexity of controlling a large number of qubits simultaneously. The authors show how error correction and logical operations can be performed on an $i\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}d\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}f\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}n\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}t\phantom{\rule{0}{0ex}}e$ number of superconducting qubits, by repetition of a unit cell and a fixed set of control components. This solution offers an integrated, basic building block for fault-tolerant quantum computation, and thus is a step forward in addressing the scalability issues in quantum-computer engineering.