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IEEE Transactions on Applied Superconductivity

Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

Ryota Kashima, Ikki Nagaoka, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, Akira Fujimaki

Published Mar 2, 2023• 4 citations
Publisher

Abstract

In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased; thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz operation. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm$^{2}$process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.

DOI
10.1109/tasc.2023.3249131

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In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased; thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz operation. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm2^{2}2process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the bit-parallel datapath is difficult because of feedback paths. We used concurrent-flow clocking and counter-flow clocking in combination to solve the timing problem at the feedback path in the datapath, and we optimized the number of JJs and pipeline stages in the register file for solving the timing issue. We designed the datapath with the cell library for the AIST 10 kA/cm2^22Advanced Process. The total number of pipeline stages, Josephson junctions, and circuit area of the designed datapath were 52, 18448, and 3.81 mm × 4.05 mm, respectively. We obtained a relatively wide bias margin of the designed datapath at the target clock frequency of 50 GHz, and it operated up to 64 GHz in on-chip high-speed testing.
Design and Implementation of a Pipelined Bit-Serial SFQ Microprocessor, CORE1β{\rm CORE}1\betaCORE1β
A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1beta, was designed and tested. The CORE1beta has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1beta8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1beta8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1beta8 microprocessors by on-chip high-speed tests.
We have designed a pipelined 8-bit-serial single-flux-quantum microprocessor with multiple ALUs, called CORE1 β. In the CORE1 β, two ALUs connected in cascade enable us to perform two calculations on serial data using a register-to-register instruction, to enhance the peak performance. In addition, we have introduced pipelining to boost the performance. Although the pipelining is a difficult technique that requires a complex design in the datapath, we have implemented a simplified pipeline with seven stages by using two techniques. One is the separation of clock signals for pipelining and bit processing, and the other is the introduction of new buffers driven by independent clock signals for reading and writing flexibly in order to ease the difficulty in timing design between the register file and the ALUs. According to the logic simulation, the peak performance of the designed microprocessor is estimated to be 1500 million operations per second with a power consumption of 3.3 mW. We have fabricated the CORE1 β chip by using the NEC 2.5 kA cm −2 niobium standard process, and confirmed the correct operations of several instructions using high-speed clocks.
We have designed and demonstrated an arithmetic logic unit (ALU) based on rapid single-flux-quantum (RSFQ) technology. The ALU has been developed toward demonstration of high-performance information processing using a general purpose microprocessor CORE e4. The target operation frequency of the ALU is 50 GHz. In this paper, we present the design and high- speed functionality test results of the ALU. The ALU can execute 10 instructions. We aimed at high frequency operation with precise timing design using logic gates synchronized to the clock signal. The ALU contains 1555 Josephson junctions (JJs) and occupies a circuit area of 0.53mm2. We have demonstrated the correct operation of the ALU using on-chip high-speed test. The estimated maximum operating frequency based on measurement results is 80 GHz.
Rapid single-flux-quantum (RSFQ) is expected to be the next generation integrated circuit technology because of its ultra-high-speed with ultra-low-power consumption. We propose datapath circuits for an 8-bit bit-parallel RSFQ microprocessor. The proposed datapath circuits process 8-bit data each clock cycle. Seven instructions are executed in the datapath, including ADD, ADDI, IN, OUT, LOADI, SRL and MOV. The datapath circuits consist of eight input ports, eight output ports, five multiplexers (MUXs), two 8-bit data registers and one 8-bit bit-parallel arithmetic logic unit (ALU). The datapath circuits contain 12 pipeline stages and 2993 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2 without considering wiring cells. We perform digital simulation of the proposed datapath circuits. The simulation results show correct operation with the assumed frequency of 20 GHz.
As part of the effort to develop a superconductive microprocessor, we constructed a rapid single flux quantum (RSFQ) 4-bit arithmetic and logic unit (ALU) in a pipelined structure. To speed up the circuit, we used a forward clocking scheme. The 4-bit ALU consisted of ten RSFQ Half Adders, four 2 /spl times/ 2 switches, and several D flip-flops. By commutating output ports of the half adder, we were able to produce AND, OR, XOR, and ADD functions. The 4-bit ALU was fabricated using the Korea Photonics Technology Institute's ten-level 1.0 kA/cm/sup 2/ Nb process. The size of the ALU was 3.0 mm /spl times/ 1.5 mm, fitting in a 5 mm /spl times/ 5 mm chip. The fabricated 1-bit ALU block was successfully tested at up to a 40 GHz clock frequency. The complete 4-bit ALU operated correctly at up to a 5 GHz clock frequency.