Abstract We developed fabrication and bonding technology of superconductive bump for massive quantum computing. A bonded test vehicle demonstrates supercurrent through 90 000 series daisy-chain. Proposed bump consists of lead-indium alloy. The bumps land onto gold pad on the opposite chip and alloy with the gold pad for supercurrent. The primary advantage of the proposed bump is the minimized damage to the quantum chip. Plasma cleaning process which may degrade sensitive components is only required for bump chips and not for quantum chips. Lower bonding temperature of 100 degrees Celsius for the proposed bump also keeps sensitive components away from degradation in high temperature.
Abstract We developed fabrication and bonding technology of superconductive bump for massive quantum computing. A bonded test vehicle demonstrates supercurrent through 90 000 series daisy-chain. Proposed bump consists of lead-indium alloy. The bumps land onto gold pad on the opposite chip and alloy with the gold pad for supercurrent. The primary advantage of the proposed bump is the minimized damage to the quantum chip. Plasma cleaning process which may degrade sensitive components is only required for bump chips and not for quantum chips. Lower bonding temperature of 100 degrees Celsius for the proposed bump also keeps sensitive components away from degradation in high temperature.
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
With the rapid development of big data, artificial intelligence, Internet of Things and other technologies, quantum computers have emerged. It has unparalleled advantages in the fields of complex problem optimization, physical system simulation and encryption. Among them, superconducting quantum computing has become the mainstream direction of quantum computer development due to its advantages of scalability and process compatibility. However, there is no mature process integration scheme for large-scale quantum computer packaging technology with more than 100 bits. In this paper, for the packaging requirements of general-purpose large-bit superconducting quantum chips, a process simulation study based on the interconnection system of low-temperature superconducting In bumps and Al bonding filaments is carried out. Through the optimization of the interconnection structure of the package box structure, SMA terminals, high-speed substrate and other interconnection structures, the parasitic capacitance-generating structure is localized, electromagnetic leakage patterns are clarified, and a multilevel interconnection scheme with good electromagnetic shielding and low loss is obtained. Optimization of In bump and Al bonding process, the interconnect optimization scheme of substrate slotting and three-wire bonding is obtained, with insertion loss > -ldB and reflection loss >-20dB. The overall insertion loss of the multilevel interconnect structure is > -3dB and reflection loss >-15dB, which meets the demand of high-quality signal transmission. The results of this study demonstrate the quantum chip signal transmission and simulation modeling method, and provide a new idea for the cross-scale finite element electromagnetic simulation of superconducting quantum chips.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.
The superconducting quantum computer is an implementation of the quantum computer and a current leader the field in terms of performance and potential for scalability to large systems. Its two main components are the superconducting microwave resonator and the quantum bit (qubit). In Chapter 1, the concept of quantum computing is introduced, and the superconducting microwave resonator is explained in depth, along with a glimpse at the qubit and a description of two level system loss, the most prominent form of loss in low-power superconducting quantum circuits. Scalability is essential to the development of fault-tolerant quantum computing, as error correction requires a large array of quantum bits. The multilayer quantum circuit architecture is rising to the forefront as a solution to many of the scalability issues facing the field today. Chapter 2 summarizes some of these scalability issues, such as the suppression of unwanted modes and materials losses, and presents an overview of multilayer architectures applied to superconducting quantum circuits. The chapter further delves into indium bump bonding, an essential technique in multilayer circuit fabrication.In Chapter 3, we experimentally demonstrate a thermocompression bonding technology between on-chip indium thin films and apply it to capped superconducting devices. These devices can be used as a building block towards a more scalable architecture: the multilayer quantum circuit. We characterize the dc and microwave performance of these bonded devices at room temperature as well as cryogenic temperatures. At 10 mK, we find a small but significant dc bond resistance of 49.2μΩ cm2. A tunnel-capped, bonded device shows minimal microwave reflections and clean transmission up to 6.8 GHz compared to a similar uncapped device, demonstrating good performance. As a proof of concept, we fabricate and measure a set of tunnel-capped superconducting resonators, demonstrating marginal deterioration in resonator performance due to the bonding procedure. This work demonstrates that thermocompression bonding between thin on-chip indium films is a useful addition to the multilayer quantum circuit toolbox, and that this technique, when applied to form the tunnel-capped superconducting device, shows a promising step towards more scalable architectures. Indium is becoming ubiquitous in superconducting microwave circuits as it continues to be widely adopted as a bonding medium. However, the loss mechanisms in superconducting indium films have not been examined until now. In Chapter 4, we characterize microwave loss in indium and aluminium/indium thin films on silicon substrates by measuring superconducting coplanar waveguide resonators and estimating the main loss parameters at powers down to the sub-photon regime and at temperatures between 10 and 450 mK. We compare films deposited by thermal evaporation, sputtering, and molecular beam epitaxy. We study the effects of heating in vacuum and ambient atmospheric pressure as well as the effects of pre-deposition wafer cleaning using hydrofluoric acid. The microwave measurements are supported by thin film metrology including secondary-ion mass spectrometry. For thermally evaporated and sputtered films, we find that two-level states (TLSs) are the dominating loss mechanism at low photon number and temperature. Thermally evaporated indium is determined to have a TLS loss tangent due to indium oxide of∼5×10−5. The molecular beam epitaxial films show evidence of formation of a substantial indium-silicon eutectic layer, which leads to a drastic degradation in resonator performance.
Low-loss cavities are important in building high-coherence superconducting quantum computers. Generating high-quality joints between parts is crucial for the realization of a scalable quantum computer using the circuit quantum electrodynamics (cQED) framework. In this paper, we adapt the technique of indium bump bonding to cQED to realize high-quality superconducting microwave joints between chips. We use this technique to fabricate compact superconducting cavities in the multilayer microwave integrated quantum circuit (MMIQC) architecture and achieve single photon quality factors over 300 × 106 or single-photon lifetimes approaching 5 ms. To quantify the performance of the resulting seam, we fabricate microwave stripline resonators in multiple sections connected by different numbers of bonds, resulting in a wide range of seam admittances. The measured quality factors combined with the designed seam admittances allow us to bound the conductance of the seam at gseam≥2×1010/(Ω m). Such a conductance should enable the construction of micromachined superconducting cavities with a quality factor of at least a billion. These results demonstrate the capability to construct very high-quality microwave structures within the MMIQC architecture.