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International Conference on Electronic Packaging Technology (ICEPT)

Simulation of Quantum Chip Packaging Based on Superconducting Material Interconnection System

Jiaxing Wang, Pengrong Lin, Yingzhuo Huang, Xiaochen Xie, Shimeng Xu, Long Zhang

Published Aug 7, 2024• 0 citations
Publisher

Abstract

With the rapid development of big data, artificial intelligence, Internet of Things and other technologies, quantum computers have emerged. It has unparalleled advantages in the fields of complex problem optimization, physical system simulation and encryption. Among them, superconducting quantum computing has become the mainstream direction of quantum computer development due to its advantages of scalability and process compatibility. However, there is no mature process integration scheme for large-scale quantum computer packaging technology with more than 100 bits. In this paper, for the packaging requirements of general-purpose large-bit superconducting quantum chips, a process simulation study based on the interconnection system of low-temperature superconducting In bumps and Al bonding filaments is carried out. Through the optimization of the interconnection structure of the package box structure, SMA terminals, high-speed substrate and other interconnection structures, the parasitic capacitance-generating structure is localized, electromagnetic leakage patterns are clarified, and a multilevel interconnection scheme with good electromagnetic shielding and low loss is obtained. Optimization of In bump and Al bonding process, the interconnect optimization scheme of substrate slotting and three-wire bonding is obtained, with insertion loss > -ldB and reflection loss >-20dB. The overall insertion loss of the multilevel interconnect structure is > -3dB and reflection loss >-15dB, which meets the demand of high-quality signal transmission. The results of this study demonstrate the quantum chip signal transmission and simulation modeling method, and provide a new idea for the cross-scale finite element electromagnetic simulation of superconducting quantum chips.

DOI
10.1109/icept63120.2024.10668742

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With the rapid development of big data, artificial intelligence, Internet of Things and other technologies, quantum computers have emerged. It has unparalleled advantages in the fields of complex problem optimization, physical system simulation and encryption. Among them, superconducting quantum computing has become the mainstream direction of quantum computer development due to its advantages of scalability and process compatibility. However, there is no mature process integration scheme for large-scale quantum computer packaging technology with more than 100 bits. In this paper, for the packaging requirements of general-purpose large-bit superconducting quantum chips, a process simulation study based on the interconnection system of low-temperature superconducting In bumps and Al bonding filaments is carried out. Through the optimization of the interconnection structure of the package box structure, SMA terminals, high-speed substrate and other interconnection structures, the parasitic capacitance-generating structure is localized, electromagnetic leakage patterns are clarified, and a multilevel interconnection scheme with good electromagnetic shielding and low loss is obtained. Optimization of In bump and Al bonding process, the interconnect optimization scheme of substrate slotting and three-wire bonding is obtained, with insertion loss > -ldB and reflection loss >-20dB. The overall insertion loss of the multilevel interconnect structure is > -3dB and reflection loss >-15dB, which meets the demand of high-quality signal transmission. The results of this study demonstrate the quantum chip signal transmission and simulation modeling method, and provide a new idea for the cross-scale finite element electromagnetic simulation of superconducting quantum chips.
Superconducting quantum computers have the advantages of mature chip processing technology,high system integration,and good scalability.However,superconducting quantum computing needs to increase the quantum integration of chips and ensure decoherence time of quantum chips to achieve fault-tolerant quantum computing.The advancement of superconducting quantum chips is analyzed,and the physical mechanism,advantages and disadvantages of superconducting quantum bus are presented,and several basic quantum bits characteristics are studied.The coupling scheme is discussed between superconducting qubits,including local and non-local coupling.Analysis results on mainstream expansion and layout schemes in recent years show that quantum algorithm programming is suitable for one-dimensional or two-dimensional arrays,while maximum entanglement and full coupling use wraparound expansion schemes to achieve large-scale,high-efficiency quantum to provied an idea for the design of the computational chip.
In recent years the interest in building quantum computers with superconducting qubits has steadily increased. Indium is one of the chosen interconnect materials for bonding qubit microchips with Josephson junctions to microelectronic resonators because indium is superconducting and ductile. Indium bump bonding is a common technique for hybridizing pixel radiation sensors to readout chips for some time; however, such detectors operate usually at room temperature. The challenge is to transfer this bonding technique to the fabrication of devices that can operate and withstand very low mKtemperatures. This paper summarizes the current challenges for implementing indium bump bonding to stacked superconducting qubit chips with a particular focus on chip parallelism and superconductivity of the interconnects. A high precision of parallelism between bonded qubit and resonator microchips is essential for minimizing signal loss, and superconducting materials such as indium are required for signal transfer. Photolithography or shadow masking techniques are commonly used to deposit severalμ\muμm-thick indium bumps on microchips. This paper outlines initial experiments to verify and optimize the indium bump deposition and flip-chip bonding for superconducting qubit chips. Stacked chip parallelism is evaluated after flip-chip bonding, the tolerance of the parallelism between stacked chips will be determined with an optical scanner, microscope and Scanning Electron Microscopy (SEM). For the superconductivity of interconnects, daisy chain chips are designed, built and flip-chip bonded. The common Under-Bump Metallization (UBM) for the adhesion of indium bumps to pixel pads requires modification with superconductive material and is investigated with resistance measurements that are taken at room temperature with a probe tester and at mK-temperature in a helium dilution refrigerator.
As one of the mainstream technique routes to implement universal quantum computing, superconducting qubit has been highly anticipated in recent years. However, the current widely-using 2D interconnect forms are not capable to meet the interconnect demand of high integration quantum processor in practical use due to wiring congestion, electromagnetic crosstalk, mechanical stress concentration, limited interior space of dilution refrigerator, etc. Therefore, quantum packaging will also need to be updated from 2D planar to 3D vertical architecture for higher integration density of superconducting qubits. In view of the current chiplet development trends in IC industry, we propose a 3D integration architecture based on the partition strategy of qubit chiplet and bus chiplet for superconducting quantum computing. This chiplet solution respectively utilizes the TSV and microbump structure in superconducting constituent material scheme to achieve low-loss intra-layer and inter-layer connection, which provides a possible technical route for modular large-scale quantum processor. To verify the feasibility of the above architecture, we design a kind of TiN-based TSV test vehicle including daisy chain structure to inspect the stabilization of DC resistance and transmission line structure for evaluation of DC/microwave signal transporting performance during the cool-down process. The TSVs in this test vehicle possess high aspect ratio (10:1,30μm30 \mu\mathrm{m}30μmdiameter) fabricated by DRIE, coating with ∼200nm TiN layer by ALD. Subsequently, Al/TiN planar wiring layer is patterned by secondary lithography and ICP process. Then morphology observation, R.T./cryogenic electrical tests are successively carried out to evaluate the performance of TSV test vehicle. SEM along with EDS reveal that the TiN coating is conformal and defect-free with nearly vertical sidewall profile. Electrical tests show that TSV structures possess satisfactory linear ohmic characteristics and a wide range of process uniformity and repeatability at R.T. Additionally, the DC resistance and S21loss amplitude both exhibit abrupt drop during the cooling process, indicating that certain degree of superconducting transition has probably occurred. Therefore, the TiN-based TSV interposer elaborated in this paper combined with indium-based flip-chip TCB methods provides the possibility to implement 3D quantum integration architecture based on chiplet design.
Superconducting quantum circuits (SQCs), composed of superconducting capacitors, inductances, Josephson junctions, and transmission lines, exhibit macroscopic quantum effects at ultra-low temperatures. Due to the extremely low dissipation of superconductors, an important application of SQCs is superconducting qubits with long coherence time. Quantum computing based on superconducting qubits is a leading physical realization method of quantum computing, which is theoretically capable of accelerating many computational problems including quantum simulation, database searching, and optimization. In the long run, to use the power of quantum computing to its full extent, universal quantum computers should be constructed with quantum error correction. In the short term, one of the most pressing targets of the superconducting quantum computing community is to demonstrate quantum advantage using noisy intermediate-scale quantum chips. Both goals rely on the increasing of the number of coupled qubits in a quantum circuit and the quality of these qubits, which dictate the breadth and the depth of a problem it can solve, respectively. The fabrication of SQCs has adopted a few manufacturing processes from conventional integrated circuits. Quantum chips containing multiple superconducting qubits can be made and packaged on a large scale. “Quantum supremacy” has been demonstrated on a quantum chip with fifty-three qubits fabricated using the flip-chip bonding technology. However, to demonstrate quantum advantage, the quality and quantity of qubits need to increase simultaneously. Dissipative channels emerge in circuit design, material preparation, chip fabrication, and working environment, limiting the lifetime of superconducting qubits. For quantum chips with tens to hundreds of qubits, the integration will also introduce extra processing steps which may degrade the qubits, and unwanted coupling to loss channels. Most of these channels are microscopically related to materials constructing the quantum chips, chip surfaces, and material interfaces. Thus, it is important to investigate the material growth and device fabrication of SQCs, and to understand the material related loss mechanisms. This review paper investigates the material related topics in superconducting quantum circuits pertinent to the quantum computing application from a comprehensive perspective. The history of SQCs is briefly mentioned, followed by the peculiar characteristics as an engineerable quantum system, and a roadmap to quantum advantage and universal quantum computing in the next a few years. Technically, the superconducting quantum computer is compared to a Schrodinger’s cat, and can be boiled down into three parts, i.e., quantum chips, the environment, and the operating system, corresponding to the cat, the box, and the observer, respectively. The material related decoherence channels of the SQCs can be sorted into four categories; each will be discussed in details. To fabricate SQCs with minimal loss, the processing technologies are elaborated, including qubit design, material selection, surface treatments, film growth, and Josephson junction, etc. Though there are general guidelines that amorphous materials should be avoided and processing induced damage should be minimized, more is to be investigated due to the emerging of new materials and new fabrication methods. The last part presents the potential application of the superconducting quantum computer and its current state of play. SQC for quantum computing is a multi-discipline research topic, demanding joint efforts from different scientific and technical areas. Materials science and device processing will play important roles along the way to quantum practicality.
Flip-chip integration offers a promising route toward scalable superconducting quantum processors and hybrid semiconductor-superconductor quantum devices. We develop a three-dimensional transmon architecture using electroplated indium in which the qubit electric field is shared nearly equally between two bump-bonded substrates while maintaining low participation at the indium-bump interface. The resulting geometry is well suited for future hybrid qubits, enabling the integration of distinct material platforms while minimizing sensitivity to bump-interface loss. Using this platform, we evaluate electroplated indium interconnects for superconducting quantum circuits. Flip-chip transmons incorporating electroplated indium bumps exhibit qubit quality factors around 10610^6106. In addition, a systematic study of coplanar-waveguide resonators is used to identify losses associated with the electroplating process. In particular, we find that surface losses associated with the gold-layer, used to enable good electric contact with the indium, is likely the primary contributor to the qubit decay rate. These results demonstrate the compatibility of electroplated indium technology with high-coherence superconducting circuits and establish a promising platform for three-dimensional hybrid quantum integration.
We have demonstrated superconducting interconnect technologies that enable a variety of flip-chip 3D integrated structures and packages compatible with high-coherence superconducting qubits. Superconducting indium micro-bumps and underbump metal (UBM) were used to join superconducting qubit chips to superconducting readout and control modules while maintaining high qubit coherence (T1, T2,echo> 20 μs) in the presence of capacitive and inductive coupling between the chips. Scanning electron microscope, X-ray, infrared and confocal microscopy were used to investigate the micro-structure, alignment accuracy, and parallelism of flip-chip qubits. The superconducting readout and control modules can accommodate both niobium and aluminum-based circuit and amplifier fabrication processes, including shadow-evaporated aluminum or Nb/Al-AlOx/Nb trilayer Josephson junctions (JJs). We present results for up to 16 active superconducting chips having trilayer junctions bonded to a passive superconducting module. The I-V characteristics and switching behavior were measured for flip-chip-connected JJ arrays with 40-20,000 JJs. Our approach maintained chip-level junction critical current and qubit coherence, demonstrating it to be a viable approach to building larger quantum computing systems. This paper also discusses packaging approaches to developing a quantum-to-classical interface in a cryogenic environment with multiple temperature stages.