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IEEE International Conference on Quantum Computing and Engineering (QCE)

Learning Zero Noise Extrapolation for Deterministic Quantum Circuits

Philip Turk, Ana Ozaki

Published Sep 1, 2022• 1 citation
Publisher

Abstract

In the current era of noisy quantum computers the reduction or correction of noise is one of the most important factors in achieving quantum supremacy. Zero-noise extrapolation (ZNE) uses noise amplification to imitate results with higher noise rates, which are then used to extrapolate a result with zero noise. In this work, we provide an intuitive explanation for ZNE by analogy of archery in windy conditions. We show how gate repetition can be used effectively for noise amplification. This is hardware- and platform-agnostic as it requires only gate-level control. We then show how machine learning may be combined with gate repetition to achieve ZNE. We define a class of quantum circuits, called deterministic, for which this method works. We compare the performance of neural networks with other extrapolation methods. Our technique is easy to implement and likely to scale well for large quantum systems.

DOI
10.1109/qce53715.2022.00046

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In the current era of noisy quantum computers the reduction or correction of noise is one of the most important factors in achieving quantum supremacy. Zero-noise extrapolation (ZNE) uses noise amplification to imitate results with higher noise rates, which are then used to extrapolate a result with zero noise. In this work, we provide an intuitive explanation for ZNE by analogy of archery in windy conditions. We show how gate repetition can be used effectively for noise amplification. This is hardware- and platform-agnostic as it requires only gate-level control. We then show how machine learning may be combined with gate repetition to achieve ZNE. We define a class of quantum circuits, called deterministic, for which this method works. We compare the performance of neural networks with other extrapolation methods. Our technique is easy to implement and likely to scale well for large quantum systems.
Quantum-gate errors are a significant challenge for achieving precision measurements on noisy intermediate-scale quantum (NISQ) computers. This paper focuses on zero-noise extrapolation (ZNE), a technique that can be implemented on existing hardware, studying it in detail and proposing modifications to existing approaches. In particular, we consider identity insertion methods for amplifying noise because they are hardware agnostic. We build a mathematical formalism for studying existing ZNE techniques and show how higher order polynomial extrapolations can be used to systematically reduce depolarizing errors. Furthermore, we introduce a method for amplifying noise that uses far fewer gates than traditional methods. This approach is compared with existing methods for simulated quantum circuits. Comparable or smaller errors are possible with fewer gates, which illustrates the potential for empowering an entirely new class of moderate-depth circuits on near term hardware.
A common approach to deal with gate errors in modern quantum-computing hardware is zero-noise extrapolation. By artificially amplifying errors and extrapolating the expectation values obtained with different error strengths towards the zero-error (zero-noise) limit, the technique aims at rectifying errors in noisy quantum computing systems. For accurate extrapolation, it is essential to know the exact factors of the noise amplification. In this article, we propose a simple method for estimating the strength of errors occurring in a quantum circuit and demonstrate improved extrapolation results. The method determines the error strength for a circuit by appending to it the inverted circuit and measuring the probability of the initial state. The estimation of error strengths is easy to implement for arbitrary circuits and does not require previous characterization of noise properties. We compare this method with the conventional zero-noise extrapolation method and show that our method leads to a more accurate calculation of expectation values on current quantum hardware, showcasing its suitability for near-term quantum computing applications. Published by the American Physical Society 2024
Zero-noise extrapolation (ZNE) is an increasingly popular technique for mitigating errors in noisy quantum computations without using additional quantum resources. We review the fundamentals of ZNE and propose several improvements to noise scaling and extrapolation, the two key components in the technique. We introduce unitary folding and parameterized noise scaling. These are digital noise scaling frameworks, i.e. one can apply them using only gate-level access common to most quantum instruction sets. We also study different extrapolation methods, including a new adaptive protocol that uses a statistical inference framework. Benchmarks of our techniques show error reductions of 18X to 24X over non-mitigated circuits and demonstrate ZNE's effectiveness at larger qubit numbers than have been tested previously. In addition to presenting new results, this work is a self-contained introduction to the practical use of ZNE by quantum programmers.
Near term quantum processors operate in a noise dominated regime, motivating error mitigation techniques that recover accurate expectation values without full fault tolerance. Zero Noise Extrapolation (ZNE) is a widely used but biased error mitigation method that lacks rigorous error bounds. Its effective application requires nontrivial technical choices, most notably the selection of noise scaling factors and extrapolation models, making ZNE sensitive to user expertise and often necessitating costly trial and error procedures. Here, we introduce Folding Free Zero Noise Extrapolation (FF-ZNE), a method that removes the need for noise factor selection by achieving effective noise amplification without circuit folding. FF-ZNE exploits isomorphic hardware layouts with distinct native noise profiles, such that executing a fixed circuit across these layouts induces controllable variations in the effective noise strength. Under a depolarizing noise model, we analytically show that the resulting extrapolation admits a fixed linear form, eliminating extrapolator choice and enabling a seamless, user independent mitigation procedure. We further propose two algorithms that identify sets of isomorphic hardware layouts on which a given circuit yields sufficiently distinct expectation values to enable reliable zero noise extrapolation. Experiments on a 133 qubit IBM Quantum device demonstrate that FF-ZNE yields mitigated expectation values with average deviations of ~6% and 4.5% for up to 50 qubit EfficientSU2 (sparse) and Hamiltonian simulation (dense) circuits, respectively. The method is thus scalable and applicable to a broad range of circuits. By eliminating noise factor and extrapolator selection, FF-ZNE transforms zero noise extrapolation from a technique requiring expert tuning into a practical, scalable, and broadly accessible error mitigation method for current quantum hardware.
Recent hundred-qubit processors represent a significant hardware advancement, but current limitations prevent effective quantum error correction (QEC), necessitating reliance on quantum error mitigation (QEM) to enhance result fidelity from quantum computers. Our paper introduces a noise-aware folding technique that enhances Zero-Noise Extrapolation (ZNE) by leveraging the noise characteristics of target quantum hardware to fold circuits more efficiently. Unlike traditional ZNE approaches assuming uniform error distribution, our method redistributes noise using calibration data based on hardware noise models. By employing a noise-adaptive compilation method combined with our proposed folding mechanism, we enhance the ZNE accuracy of quantum gate-based computing using superconducting quantum computers. This paper highlights the uniqueness of our method, summarizes noise accumulation, presents the scaling algorithm, and compares the reliability of our method with those of existing models using linear extrapolation model. Experimental results show that compared to existing folding methods, our approach achieved up to a 23.6% improvement on quantum computer simulators and up to a 44.8% improvement on real quantum computers, with statistical confidence intervals indicating stable performance gains across circuit scales.
Increasing the utility of currently available Noisy Intermediate-Scale Quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors. In this work we propose a novel Cyclic Layout Permutations-based Zero-Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for an nnn-qubit circuit CLP-ZNE requires execution of only O(n)O(n)O(n) and at most O(n2)O(n^2)O(n2) different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of n=12n=12n=12 qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. By demonstrating the ability to mitigate noise of real hardware specifications, including both depolarizing and T1/T2T_1/T_2T1​/T2​ relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.