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arXiv:2603.13949

Folding-Free Zero-Noise Extrapolation by Layout-induced Noise Diversity

Debarthi Pal, Yogesh Simmhan

quant-phcs.ETSubmitted Mar 14, 2026• Announced Mar 17, 2026• 0 citations
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Abstract

Near term quantum processors operate in a noise dominated regime, motivating error mitigation techniques that recover accurate expectation values without full fault tolerance. Zero Noise Extrapolation (ZNE) is a widely used but biased error mitigation method that lacks rigorous error bounds. Its effective application requires nontrivial technical choices, most notably the selection of noise scaling factors and extrapolation models, making ZNE sensitive to user expertise and often necessitating costly trial and error procedures. Here, we introduce Folding Free Zero Noise Extrapolation (FF-ZNE), a method that removes the need for noise factor selection by achieving effective noise amplification without circuit folding. FF-ZNE exploits isomorphic hardware layouts with distinct native noise profiles, such that executing a fixed circuit across these layouts induces controllable variations in the effective noise strength. Under a depolarizing noise model, we analytically show that the resulting extrapolation admits a fixed linear form, eliminating extrapolator choice and enabling a seamless, user independent mitigation procedure. We further propose two algorithms that identify sets of isomorphic hardware layouts on which a given circuit yields sufficiently distinct expectation values to enable reliable zero noise extrapolation. Experiments on a 133 qubit IBM Quantum device demonstrate that FF-ZNE yields mitigated expectation values with average deviations of ~6% and 4.5% for up to 50 qubit EfficientSU2 (sparse) and Hamiltonian simulation (dense) circuits, respectively. The method is thus scalable and applicable to a broad range of circuits. By eliminating noise factor and extrapolator selection, FF-ZNE transforms zero noise extrapolation from a technique requiring expert tuning into a practical, scalable, and broadly accessible error mitigation method for current quantum hardware.

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Near term quantum processors operate in a noise dominated regime, motivating error mitigation techniques that recover accurate expectation values without full fault tolerance. Zero Noise Extrapolation (ZNE) is a widely used but biased error mitigation method that lacks rigorous error bounds. Its effective application requires nontrivial technical choices, most notably the selection of noise scaling factors and extrapolation models, making ZNE sensitive to user expertise and often necessitating costly trial and error procedures. Here, we introduce Folding Free Zero Noise Extrapolation (FF-ZNE), a method that removes the need for noise factor selection by achieving effective noise amplification without circuit folding. FF-ZNE exploits isomorphic hardware layouts with distinct native noise profiles, such that executing a fixed circuit across these layouts induces controllable variations in the effective noise strength. Under a depolarizing noise model, we analytically show that the resulting extrapolation admits a fixed linear form, eliminating extrapolator choice and enabling a seamless, user independent mitigation procedure. We further propose two algorithms that identify sets of isomorphic hardware layouts on which a given circuit yields sufficiently distinct expectation values to enable reliable zero noise extrapolation. Experiments on a 133 qubit IBM Quantum device demonstrate that FF-ZNE yields mitigated expectation values with average deviations of ~6% and 4.5% for up to 50 qubit EfficientSU2 (sparse) and Hamiltonian simulation (dense) circuits, respectively. The method is thus scalable and applicable to a broad range of circuits. By eliminating noise factor and extrapolator selection, FF-ZNE transforms zero noise extrapolation from a technique requiring expert tuning into a practical, scalable, and broadly accessible error mitigation method for current quantum hardware.
Increasing the utility of currently available Noisy Intermediate-Scale Quantum (NISQ) devices requires developing efficient methods to mitigate hardware errors. In this work we propose a novel Cyclic Layout Permutations-based Zero-Noise Extrapolation (CLP-ZNE) protocol for such a task. The method leverages the inherent non-uniformity of gate errors in NISQ hardware to extrapolate the expectation value, averaged over cyclic circuit layout permutations, to the level of zero noise. In contrast to the previous layout permutation based approaches, for an nnn-qubit circuit CLP-ZNE requires execution of only O(n)O(n)O(n) and at most O(n2)O(n^2)O(n2) different circuit layouts for circuits of one-dimensional and arbitrary connectivity, respectively. When benchmarked against noise channels modeling the IBM Torino quantum computer, the method reduces a typical error in expectation values of n=12n=12n=12 qubit circuits by an order of magnitude, outperforming standard unitary folding ZNE. By demonstrating the ability to mitigate noise of real hardware specifications, including both depolarizing and T1/T2T_1/T_2T1​/T2​ relaxation processes, these results give evidence for the applicability of CLP-ZNE to present-day NISQ processors.
Recent hundred-qubit processors represent a significant hardware advancement, but current limitations prevent effective quantum error correction (QEC), necessitating reliance on quantum error mitigation (QEM) to enhance result fidelity from quantum computers. Our paper introduces a noise-aware folding technique that enhances Zero-Noise Extrapolation (ZNE) by leveraging the noise characteristics of target quantum hardware to fold circuits more efficiently. Unlike traditional ZNE approaches assuming uniform error distribution, our method redistributes noise using calibration data based on hardware noise models. By employing a noise-adaptive compilation method combined with our proposed folding mechanism, we enhance the ZNE accuracy of quantum gate-based computing using superconducting quantum computers. This paper highlights the uniqueness of our method, summarizes noise accumulation, presents the scaling algorithm, and compares the reliability of our method with those of existing models using linear extrapolation model. Experimental results show that compared to existing folding methods, our approach achieved up to a 23.6% improvement on quantum computer simulators and up to a 44.8% improvement on real quantum computers, with statistical confidence intervals indicating stable performance gains across circuit scales.
Quantum computers in the NISQ era are prone to noise. A range of quantum error mitigation techniques has been proposed to address this issue. Zero-noise extrapolation (ZNE) stands out as a promising one. ZNE involves increasing the noise levels in a circuit and then using extrapolation to infer the zero noise case from the noisy results obtained. This paper presents a novel ZNE approach that does not require circuit folding or noise scaling to mitigate depolarizing and/or decoherence noise. To mitigate depolarizing noise, we propose leveraging the extreme/infinite noisy case, which allows us to avoid circuit folding. Specifically, the circuit output with extreme noise becomes the maximally mixed state. We show that using circuit-reliability metrics, simple linear extrapolation can effectively mitigate depolarizing noise. With decoherence noise, different states decay into the all-zero state at a rate that depends on the number of excited states and time. Therefore, we propose a state- and latency-aware exponential extrapolation that does not involve folding or scaling. When dealing with a quantum system affected by both decoherence and depolarizing noise, we propose to use our two mitigation techniques in sequence: first applying decoherence error mitigation, followed by depolarizing error mitigation. A common limitation of ZNE schemes is that if the circuit of interest suffers from high noise, scaling-up noise levels could not provide useful data for extrapolation. We propose using circuit-cut techniques to break a large quantum circuit into smaller sub-circuits to overcome this limitation. This way, the noise levels of the sub-circuits are lower than the original circuit, and ZNE can become more effective in mitigating their noises.
As quantum computing advances towards practical applications, reducing errors remains a crucial frontier for developing near-term devices. Errors in the quantum gates and quantum state readout could result in noisy circuits, which would prevent the acquisition of the exact expectation values of the observables. Although ultimate robustness to errors is known to be achievable by quantum error correction-based fault-tolerant quantum computing, its successful implementation demands large-scale quantum processors with low average error rates that are not yet widely available. In contrast, quantum error mitigation (QEM) offers more immediate and practical techniques, which do not require extensive resources and can be readily applied to existing quantum devices to improve the accuracy of the expectation values. Here, we report the implementation of a zero-noise extrapolation-based error mitigation technique on a silicon spin qubit platform. This technique has recently been successfully demonstrated for other platforms such as superconducting qubits, trapped-ion qubits, and photonic processors. We first explore three methods for amplifying noise on a silicon spin qubit: global folding, local folding, and pulse stretching, using a standard randomized benchmarking protocol. We then apply global folding-based zero-noise extrapolation to the state tomography and achieve a state fidelity of 99.96% (98.52%), compared to the unmitigated fidelity of 75.82% (82.16%) for different preparation states. The results show that the zero-noise extrapolation technique is a versatile approach that is generally adaptable to quantum computing platforms with different noise characteristics through appropriate noise amplification methods.
Reliable benchmarking of Quantum Error Mitigation (QEM) requires distinguishing genuine improvements from artefacts of the post-processing arithmetic. In this paper, we expose a failure mode in Richardson Zero-Noise Extrapolation (ZNE), a widely used technique routinely (and often implicitly) relied upon in benchmarks and experiments. When noise amplification operates beyond usable signals - a regime that is quickly reached on current hardware for non-trivial circuits - we show that the extrapolation no longer reflects the underlying physics, but collapses into a fixed rescaling of a single noisy measurement, producing a bogus apparent improvement that is independent of noise amplification. This poses a rarely considered threat to the validity of many empirical evaluations in quantum computing. Measurements on real hardware (IQM Euro-Q-Exa) confirm this collapse with ordinary folding alone: as circuit depth erodes the signal, the reported estimate decouples from the truth and overshoots the ideal by up to 21%. We further introduce a matched-cost "garbage-folding" negative control that carries no usable signal yet reports a larger apparent improvement than genuine folding - showing that the magnitude of an improvement is not evidence of its correctness - alongside a zero-cost check flagging the artefact from data a benchmark already holds. We distil both into a short reporting checklist for ZNE benchmarks.
We present a simple, malleable and low-overhead approach for improving generic biased quantum error mitigation (QEM) methods, achieving up to 15% fidelity improvements over standard QEM on 100-qubit circuits with up to 2000 entangling gates. We do so by constructing verifiable benchmark circuits which mirror the application circuit's native-gate structure and thus noise profile. These circuits can be used to benchmark and mitigate the bias of the underlying error mitigation method, requiring only the application circuit and hardware native gate set. We present two methods for generating benchmark circuits; one is agnostic to the target hardware at the expense of a small overhead of single-qubit gates, while the other is specific to the IBM superconducting hardware and has no gate overhead. As a corollary, we introduce benchmarked-noise zero-noise extrapolation (bnZNE) as a simple adaptation of zero-noise extrapolation (ZNE), one of the most popular error mitigation methods. We consider as an example the bias-mitigated ZNE and bnZNE of Trotterized Hamiltonian simulations, observing that our approaches outperform standard ZNE using both small-scale classical simulations and 100-qubit utility-scale experiments on the IBM superconducting hardware. We consider the measurement of both single-site observables as well as two-site correlations along a one-dimensional qubit chain. We also provide a software package for implementing the error mitigation techniques used in this research.