This paper presents a 28 nm cryo-CMOS system-on-chip (SoC) for the dispersive readout of superconducting qubits operating between 6.5-8.1 GHz at 4 K. The SoC includes a quadrature VCO and a full zero-IF transmitter and receiver chain, including 200 MS/s7-bit DACs, ADCs, and digital. It can generate pulses up to 640 ns duration, and it attains a very low-power readout operation (9.8 mW) compared to its counterparts with 0.5-0.6 dB noise figure, 65–89 dB gain, and -71 dBm maximum TX output power at 4 K. Furthermore, with its duty-cycled mode, the SoC reduces the average power dissipation for the readout application.
This paper presents a cryo-CMOS readout SoC based on a homodyne demodulation architecture with an integrating receiver. The homodyne receiver module for each qubit employs a dedicated local LO generator for a coherent detection under a frequency-division multiplexed multi-qubit readout environment. To mitigate the conventional issues of the homodyne demodulation in wireless communications, such as 1/f noise and DC offset by LO leakage, the proposed receiver incorporates effective calibration schemes by utilizing the specific operating conditions of the superconducting qubits. The implemented chip in 40 nm CMOS is tested at 4 K in a dilution refrigerator under an emulated SNR environment of superconducting qubit readout, i.e. -70 dBm input with a noise floor of -148 dBm/Hz. Measurement shows that circuit-only fidelity reaches 99% in 200 ns with an ideal single tone RF input. A back-to-back test using an on-chip 4-tone transmitter shows a 93 % circuit-only fidelity with 400 ns integration.
This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.
Cryogenic CMOS (Cryo-CMOS) ASICs have drawn increasing attention with great potential in scaling down the quantum computing (QC) platform. Recently, several cryoCMOS ASICs have been presented in the literature, including the qubit state readout ASICs [1–4] and state controller ASICs [5–8]. For readout ASICs, the quadrature down conversion architecture is widely adopted, with the power consumption ranging from 20mW [1] to 75mW [2]. Also, significant progress has been made in reducing the power consumption of qubit controllers. The controller in [5] consumes a power of <4 mW/qubit under active control, when controlling a superconducting quantum computing unit cell. Nevertheless, it remains a long-term goal to reduce the power consumption and promote the integration level of readout/controller ASICs, in consideration of the increasing requirement on qubit number and the limited cooling power provided by the dilution refrigerator.
This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm2. The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at
9.98 μs are also successfully observed using the proposed chipset at 3.5 K.
Superconducting qubits are promising candidates for building scalable quantum computers, but they require efficient and flexible readout systems that operate at cryogenic temperatures. This article presents a cryo-CMOS analog baseband (ABB) for superconducting qubits readout, which targets flexibly reconfigurable gain, center frequency, and bandwidth. The ABB achieves power and area reduction by integrating programmable-gain amplifiers and filters in one block and by using differential capacitors rather than single-ended ones. The differential-mode gain and common-mode stability of the low-pass filter are improved by negative-impedance inverters. Implemented in 28-nm Bulk CMOS technology, the ABB occupies an active area of 0.016 mm2. It has a tunable gain range from 10.7 to 42.5 dB, a center frequency from 101 to 189 MHz, and a bandwidth from 1.3 to 2.8 MHz. Thus, the ABB enables high-fidelity and low-power readout of superconducting qubits for future large-scale quantum computers.
Cryogenic CMOS control and readout circuits tightly interfaced with the qubits have emerged as a promising solution for future quantum computers with tens-of-thousands to millions of qubits [1] –[5]. A lownoise cryo-CMOS receiver at
3−4 K integrated tightly with the lowcryogenic quantum processor can relax or even potentially eliminated the need for the HEMT LNA, and keep the whole control loop at cryogenic temperature, hence avoiding any high-speed interconnects to room temperature (Fig. 1). Additionally, wide bandwidths in the receiver enables qubit-multiplexing, where qubits can be frequency multiplexed with a spacing of
10MHz−40MHz, allowing anywhere from 10’s-100’s of qubits to be packed in to a single readout line with gigahertz-scale bandwidths. A second critical metric is power consumption, since the cooling power available in a typical dilution refrigerator is limited to a few watts at
3−4 K. Therefore, the control and readout circuits should be designed with low power consumption, projected to be
<1 mW per qubit (Fig. 1). While there has been initial progress in the design of cryo-CMOS readout systems, a leap forward is required in their overall power consumption to be viable for future quantum systems. In this work, we showcase the design and implementation of the first sub-mWper-qubit cryo-CMOS RX - a wideband, I/Q-downconversion,
4 K receiver for qubit readout that achieves
>1.9GHz of IF bandwidth with
>50 dB conversion gain and
0.7 dB NF while consuming only
17 mW of power consumption, thanks to various design techniques including near-threshold operation and low-1/f-noise passive mixers, representing
3−5× lower power consumption than prior works [2]–[3] while achieving similar noise, BW and gain performance. In addition, we demonstrate a real-time qubit read-out measurement by integrating our cryogenic-CMOS receiver with a transmon qubit.