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Journal of Physics Conference Series

Compact Stochastic Computing Circuits Using the Latching Function of RSFQ Circuits for Computing Polynomials

Koki Wada, Nobutaka Kito

Published Aug 1, 2022• 1 citation
Publisher

Abstract

Abstract Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.

DOI
10.1088/1742-6596/2323/1/012032

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Abstract Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.
Abstract This study proposes a design method for RSFQ stochastic computing (SC) circuits. The method generates circuits with improved accuracy compared to a previously proposed method. This improvement in accuracy is realized using partial duplication. SC requires a large number of clock cycles to obtain a calculation result owing to lengthy observation of the output bitstream. The proposed method can either enhance the accuracy while maintaining the latency or mitigate the latency in clock cycles while maintaining the same accuracy. The design method duplicates a small part of the original circuit considering effectiveness for accuracy improvement. Therefore, the number of additional gates in circuits designed with the proposed method is negligible. The evaluation results indicate that, compared to circuits without duplication, the mean absolute error of circuits including one duplicated part designed with the method is reduced to approximately 60%.
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Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.
Abstract A superconducting single-flux-quantum (SFQ) circuit is suitable for stochastic computation that represents information in terms of the probability of ‘1’s in a finite-bit-length number train, due to its high-speed operation. In this paper, we demonstrate a matrix multiplier based on the SFQ logic circuits and superconductive random number generators (SRNGs). The stochastic multiplier required for the matrix product calculation is implemented using an AND gate. The stochastic adder is implemented by a multiplexer where the random number train generated by the SRNG is utilized as a control signal. We implemented 2 × 2 matrix multiplier targeting a frequency of 50 GHz, using the 10 kA cm −2 Nb 4-layer superconductor circuit fabrication process. Numerical calculation results show that the designed stochastic matrix multiplier can multiply with a computational error of 1.12% when the input stochastic numbers are 1000-bit number trains. In the measurements, the input stochastic numbers were also generated by SRNGs, and the operation of the test circuit was verified. We experimentally demonstrated the correct operation of the matrix multiplier, and the obtained calculation errors agreed with theoretical values. To the best of our knowledge, this is the first demonstration of stochastic arithmetic operation using SFQ circuits.
We present a new design technique of rapid single-flux-quantum (RSFQ) logic gates for low-noise, high-speed operation. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed reduced timing jitter by ~5% in association with small delay time, sharpened BER curves, and improvement in operating margins by 2-3% compared to the standard design. We fabricated 2-bit shift registers using the noise reduction technique. We obtained sharp BER curves from the measurement. The proposed method indicated that it gave wide margins.
A method for converting a CMOS logic circuit design to an efficient RSFQ design, which minimizes the number of flip-flops during conversion, is proposed. In an RSFQ circuit, each data input terminal of a logic gate has latching function, and the function is enabled or disabled depending on the order of the arrivals of the data pulse and the corresponding clock pulse. The number of flip-flops is minimized by the use of the latching functions through arrangement of the order of pulse arrivals of each gate and also by circuit retiming. A conversion tool based on the proposed method has been developed. Conversion results of CMOS benchmark circuits show that most of the flip-flops in the circuits are eliminated by the proposed method. A 4-bit RSFQ processor was successfully designed by an existing CMOS design tool and the developed conversion tool.