Abstract This study proposes a design method for RSFQ stochastic computing (SC) circuits. The method generates circuits with improved accuracy compared to a previously proposed method. This improvement in accuracy is realized using partial duplication. SC requires a large number of clock cycles to obtain a calculation result owing to lengthy observation of the output bitstream. The proposed method can either enhance the accuracy while maintaining the latency or mitigate the latency in clock cycles while maintaining the same accuracy. The design method duplicates a small part of the original circuit considering effectiveness for accuracy improvement. Therefore, the number of additional gates in circuits designed with the proposed method is negligible. The evaluation results indicate that, compared to circuits without duplication, the mean absolute error of circuits including one duplicated part designed with the method is reduced to approximately 60%.
Abstract This study proposes a design method for RSFQ stochastic computing (SC) circuits. The method generates circuits with improved accuracy compared to a previously proposed method. This improvement in accuracy is realized using partial duplication. SC requires a large number of clock cycles to obtain a calculation result owing to lengthy observation of the output bitstream. The proposed method can either enhance the accuracy while maintaining the latency or mitigate the latency in clock cycles while maintaining the same accuracy. The design method duplicates a small part of the original circuit considering effectiveness for accuracy improvement. Therefore, the number of additional gates in circuits designed with the proposed method is negligible. The evaluation results indicate that, compared to circuits without duplication, the mean absolute error of circuits including one duplicated part designed with the method is reduced to approximately 60%.
Abstract Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.
Quantum computing is considered a promising platform for next-generation large-scale computing. Although fully scalable quantum computers are still under development, quantum accelerators already offer a practical means to test, evaluate, and better understand quantum computation. Existing simulators provide valuable tools, but they typically rely on deterministic arithmetic and often incur significant computational overhead. To address these limitations, we developed a quantum computing simulator based on bipolar stochastic arithmetic, designed with two goals in mind. First, stochastic computation enables flexible, on-demand control of simulation precision and runtime. Second, stochastic circuits generally require significantly less hardware area than their deterministic counterparts. In our approach, quantum states and operations are encoded using bipolar stochastic bitstreams, allowing quantum circuits to be simulated using lightweight stochastic logic. We implement a representative set of quantum circuits and evaluate the simulator with respect to accuracy and required stream length. The results demonstrate that stochastic simulation yields satisfactory accuracy for small quantum circuits in software, and with improved error-correction techniques, it has the potential to serve as an efficient alternative to conventional quantum simulators.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.
Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.
Quantum computers are inhibited by physical errors that occur during computation. For this reason, the development of increasingly sophisticated error characterization and error suppression techniques is central to the progress of quantum computing. Error distributions are considerably influenced by the precise gate scheduling across the entire quantum processing unit. To account for this holistic feature, we may ascribe each error profile to a (clock) cycle, which is a scheduled list of instructions over an arbitrarily large fraction of the chip. A celebrated technique known as randomized compiling introduces some randomness within cycles' instructions, which yields effective cycles with simpler, stochastic error profiles. In the present work, we leverage the structure of cycle benchmarking (CB) circuits as well as known Pauli channel estimation techniques to derive a method, which we refer to as cycle error reconstruction (CER), to estimate with multiplicative precision the marginal error distribution associated with any effective cycle of interest. The CER protocol is designed to scale for an arbitrarily large number of qubits. Furthermore, we develop a fast compilation-based calibration method, referred to as stochastic calibration (SC), to identify and suppress local coherent error sources occurring in any effective cycle of interest. We performed both protocols on IBM-Q 5-qubit devices. Via our calibration scheme, we obtained up to a 5-fold improvement of the circuit performance.
Various emerging technologies promise advantages with respect to integration density, performance or power consumption, at the cost of approximate or probabilistic behavior. Approximate computing, where limited computational inaccuracies are tolerated at the system or application level is therefore of increasing interest. This paper investigates the use of stochastic computing (SC) as a tool for approximate simulation of probabilistic behavior. SC has the advantage of processing probabilities directly at very low hardware cost. It also allows accuracy to be traded for run-time in a natural way (progressive precision). AS a target technology to be simulated, we choose quantum computing circuits, whose behavior is inherently probabilistic and cannot be efficiently simulated by conventional (classical) means. We show how complex operations such as superposition and entanglement can be handled by SC. Finally, we report experimental results on software-based simulation of representative quantum circuits, both stand-alone and FPGA-supported. The results show that the SC implementations are orders of magnitude more compact than those based on classical circuits. Accurate results may require very long simulation runs, but run-times can be reduced by exploiting SC's progressive precision property.