We report on the measurement of the high frequency properties of a planar Penning ion trap fabricated on a chip. Two types of chips have been measured: the first manufactured by photolithographic metal deposition on a p-doped silicon substrate and the second made with printed circuit board technology on an alumina substrate. The input capacitances and the admittances between the different trap's electrodes play a critical role in the electronic detection of the trapped particles. The measured input capacitances of the photolithographic chip amount to 65-76 pF, while the values for the printed circuit board chips are in the range of 3-5 pF. The latter are small enough for detecting non-destructively a single trapped electron or ion with a specifically tuned LC resonator. We have also measured a mutual capacitance of ∼85 fF between two of the trap's electrodes in the printed circuit board chip. This enables the detection of single, or very few, trapped particles in a broader range of charge-to-mass ratios with a simple resistor on the chip. We provide analytic calculations of the capacitances and discuss their origin and possible further reduction.
We report on the measurement of the high frequency properties of a planar Penning ion trap fabricated on a chip. Two types of chips have been measured: the first manufactured by photolithographic metal deposition on a p-doped silicon substrate and the second made with printed circuit board technology on an alumina substrate. The input capacitances and the admittances between the different trap's electrodes play a critical role in the electronic detection of the trapped particles. The measured input capacitances of the photolithographic chip amount to 65-76 pF, while the values for the printed circuit board chips are in the range of 3-5 pF. The latter are small enough for detecting non-destructively a single trapped electron or ion with a specifically tuned LC resonator. We have also measured a mutual capacitance of ∼85 fF between two of the trap's electrodes in the printed circuit board chip. This enables the detection of single, or very few, trapped particles in a broader range of charge-to-mass ratios with a simple resistor on the chip. We provide analytic calculations of the capacitances and discuss their origin and possible further reduction.
This thesis presents the development of a novel type of planar Penning Trap known as the Geonium Chip. The thesis describes a wide array of experimental work done in the laboratory in different topics in order to build the trap. The main focus is a detailed research of the high frequency properties of the trap and the design of new methods of detection of the trapped particles. The Geonium Chip aims at developing a practical planar, scalable Penning Trap making it suitable for new uses and technologies, such as mass spectrometry and single microwave photon detection. This thesis is mainly focussed on the high frequency properties of the trap, essential to the design of experiment and specially of the chip itself. A new trapped particle detection system is investigated, which replaces the narrow band superconducting resonator normally used in Penning trap experiments by a common SMD resistor. This represents a considerable reduction of the size of the set-up. Moreover, it is an important progress with respect to previous resonator systems, since it is able to work in a broad range of frequencies - a severe limitation of current Penning traps in applications such as mass spectrometry
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
We report on the realization of a chip-based multipole ion trap manufactured using microelectromechanical systems technology, requiring minimal manual alignment of the electrodes. It provides ion confinement in an almost field-free volume between two planes of radiofrequency electrodes, deposited on glass substrates, which allows for optical access to the trap. An analytical model of the effective trapping potential is presented and compared with numerical calculations. Stable trapping of argon ions is achieved, and a lifetime of 16 s is measured. Electrostatic charging of the chip surfaces is studied and found to agree with a numerical estimate.
Qubits encoded in the spin of trapped electrons have been proposed as a promising novel platform for quantum information processing. While trapping of electrons has been largely carried out in Penning traps for precision measurement purposes, it is desirable to use linear Paul traps instead, leaning on the successes of trapped ion quantum processors. Here we present a Paul trap for electrons made of a single printed circuit board. Our approach requires no assembly and the rigid design minimizes manufacturing intolerances. We characterize the trap performance and observe trapped electron lifetimes of 2.13 ms and secular frequencies of up to 90 MHz.
Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.
Surface electrode ion trap on different substrates (i.e., high-resistivity (HR) silicon, silicon with grounding plane, and glass) are designed and fabricated. Performance comparison of these substrates is carried out in terms of leakage current, parasitic capacitance and RF loss. It is found that ion trap fabricated on glass has superior RF performance, but the leakage current between center electrodes can be as high as 10-8A, limiting the maximum RF voltage allowed in the ion trap. For traps on silicon with grounding plane, on-chip insertion loss (S21) is reduced by ~4.6 dB and resonance peak power after packaging is improved by ~10 dBm, compared with traps on HR silicon. Ion trapping operation is carried out on glass traps, where a single ion can be trapped for several hours with Doppler cooling.