Surface electrode ion trap on different substrates (i.e., high-resistivity (HR) silicon, silicon with grounding plane, and glass) are designed and fabricated. Performance comparison of these substrates is carried out in terms of leakage current, parasitic capacitance and RF loss. It is found that ion trap fabricated on glass has superior RF performance, but the leakage current between center electrodes can be as high as 10-8A, limiting the maximum RF voltage allowed in the ion trap. For traps on silicon with grounding plane, on-chip insertion loss (S21) is reduced by ~4.6 dB and resonance peak power after packaging is improved by ~10 dBm, compared with traps on HR silicon. Ion trapping operation is carried out on glass traps, where a single ion can be trapped for several hours with Doppler cooling.
Surface electrode ion trap on different substrates (i.e., high-resistivity (HR) silicon, silicon with grounding plane, and glass) are designed and fabricated. Performance comparison of these substrates is carried out in terms of leakage current, parasitic capacitance and RF loss. It is found that ion trap fabricated on glass has superior RF performance, but the leakage current between center electrodes can be as high as 10-8A, limiting the maximum RF voltage allowed in the ion trap. For traps on silicon with grounding plane, on-chip insertion loss (S21) is reduced by ~4.6 dB and resonance peak power after packaging is improved by ~10 dBm, compared with traps on HR silicon. Ion trapping operation is carried out on glass traps, where a single ion can be trapped for several hours with Doppler cooling.
Among the various physical systems for quantum bit (qubit) implementation, trapped ion has drawn significant attention due to its long coherence time (in the second range) and high gate fidelity (>99.99% for single qubit gate). After years of careful development, the ion trap, from mechanically assembled linear trap to lithography-defined surface electrode ion trap, is compatible with CMOS fabrication, which opens the door for the high-resolution, high-repeatability and large-scale ion trap manufacturing. To date, the number of fully connected ion qubits in state-of-the-art ion trapping devices is ~10. However, to scale close to or even beyond the noisy intermediate-scale quantum regime (NISQ, ~100 ions), some challenges remain. One such challenge is to maintain the delicate control of multiple components over individual ion with increasing ion number. In such context, this thesis is committed to boost the scalability of ion trap by integrating advanced 3D interconnects (e.g., through silicon via) and other functional modules (e.g., silicon photonics and multilayer metallization). 3D interconnects are integrated in the half space underneath surface electrode, to replace conventional wire bonding that extends out of the surface. Silicon photonics (grating coupler and waveguide) in place of bulk optics and lenses are used for on-chip light routing and emission. Multilayer metallization is used to maintain the overall RF performance and enable high-density interconnection where necessary. Firstly, surface electrode ion traps on different substrates (namely high resistivity silicon, silicon with grounding plane and glass) are designed and fabricated. Standard CMOS back-end-of-line fabrication process on 12-inch wafer platform is employed. The electrical performances of different traps are compared in terms of leakage current (I-V), parasitic capacitance (C-V), on-chip RF loss (S-parameter) and post-packaging resonance. Though the leakage (at the order of 10-8 A) between neighboring electrodes is relatively high, ion trap on glass substrate demonstrates extremely small capacitance (<1 pF) and low RF loss (insertion loss of <0.05 dB at RF frequency of 50 MHz), as compared to the silicon counterparts. This is mainly due to excellent insulation property of glass. Following that, ion trapping test is performed on the glass trap and ions are successfully confined with an averaged lifetime of ~30 minutes (compatible with the 10-11 mbar vacuum level (10-13 Pa)). To simultaneously leverage the dielectric property of glass and the microfabrication compatibility of silicon, the integration of silicon ion trap and glass interposer is performed, between which TSV is used to build the vertical interconnection. Due to the incorporation of TSV, the original wire bonding pads as well as the connection circuits on the surface electrodes can be eliminated. As a result, the form factor of TSV integrated trap is reduced by ~10 times. Correspondingly, the parasitic capacitance between neighboring electrodes is reduced from >24 pF to 3 pF. Similarly, the insertion loss of TSV integrated trap drops to 0.11 dB, in sharp comparison to the previous traps on silicon substrates (up to 2.4 dB). Analytical models are built to respectively characterize the electrode capacitance and overall power loss, and a good agreement is achieved between the model and the measurement result. In addition, since TSV is located in the half space underneath the surface electrodes, the electrodes geometry design is enabled with high flexibility. Meanwhile, the laser obstruction issue due to the stick-out bonding wires has been resolved. In terms of the ion trapping performance, both the heating rate (17 quanta/ms for an axial frequency of 300 kHz) and the lifetime (~30 minutes) of TSV trap are comparable with non-cryogenic traps of similar dimensions. Moreover, a customized CPGA with patterned redistribution layer is used to locate TSV integrated trap directly in the absence of glass interposer, facilitating high-efficiency thermal management and upgrading the packaging flexibility. At the next stage, the co-integration of other functional modules such as silicon photonics and multilayer metallization with TSV trap is investigated. In silicon photonics module, waveguide and grating coupler are on-chip introduced in place of bulk optics to achieve localized light routing and emission. In multilayer metallization module, as a first step, a grounding plane is incorporated into TSV trap to shield the silicon substrate from RF signal, in which specific windows are patterned onto the plane to accommodate TSV and allow the transmission of lights. The compatibility between TSV/multilayer metallization and waveguide/grating coupler for electrical and optical (E/O) signal routing is demonstrated. The preliminary test result based on wafer frontside shows that a ~40% capacitance reduction is achieved, and the insertion loss further drops to 0.06 dB, close to the performance of glass trap. In addition, the simulation results on photonics components indicate that an overall coupling efficiency of <30 dB is obtained from the input fiber to the ion through the photonics circuit. However, the measured power loss for light with wavelength of 1092 nm is as high as 50 dB. The deviation between the simulation and measurement is largely due to the fabrication imperfection and the resultant sloped grating coupler profile. This thesis focuses on the scalability enhancement of ion trap by integrating TSV, silicon photonics and multilayer metallization into conventional ion trap. The results are promising and pave the way for the future large scale quantum computing based on trapped ion.
This article presents the design and development of surface electrode ion traps on glass and Si substrates and their radio frequency (RF) characterizations and performance benchmarking. In this case, the ion trap on glass shows superior performances in all necessary criteria. In terms of RF characterizations, ion traps on glass have aQfactor of greater than 900. This is significantly higher than theQfactor of its silicon counterparts, which are around 20–300. Such a highQfactor results in power spectral density (PSD) of greater than 10 W/MHz. On the other hand, ion traps on silicon produce PSD values of lower than 3 W/MHz. In terms of RF performance, the ion trap on glass shows insertion loss lower than 0.2 dB at 60 MHz. This is more superior to insertion loss values of ion traps on silicon, which are around 1–4 dB. The ion-traps metallization is developed using three metallization layers (0.1-μmTi barrier layer, 2.5–3.7-μmCu, and 0.3-μmAu) on top of the dielectric. The on-chip resonance condition can be maintained upon packaging integration. The laser optical setup for ion trapping is verified to capture a single88Sr+ion.
Surface electrode ion trap is a promising candidate for quantum information processing (QIP), due to its feasibilities towards large-scale fabrication and on-chip electro-optical integration. In this paper, surface electrode ion traps on different substrates (e.g., high-resistivity silicon, silicon with ground plane and glass) are fabricated, assembled and tested. To simultaneously leverage the established fabrication technique of silicon and superior insulation property of glass, we further demonstrate a novel ion trap design with heterogenous integration of silicon and glass, acting respectively as ion trap and interposer substrates. The vertical connection between the silicon ion trap and the glass interposer is achieved by through silicon via (TSV) and micro bump. This silicon-glass integrated system advances the development of ion trap and enriches the toolbox of scalable QIP.
Ion trap is a promising approach to realizing scalable quantum computer as it presents high coherence time. Silicon, due to its manufacturability, is being considered as a potential substrate to fabricate complex ion-trap designs towards trap miniaturization and on-chip integration of electronics and optics. However, Si ion traps need proper structural design to reduce the substrate RF loss. In this paper, high-resistivity Si substrate materials has been utilized to fabricate surface electrode ion trap. Its DC and RF properties has been investigated and compared to the ion trap fabricated on sapphire substrate, which is one of the most established substrate material for trap fabrication.
Surface electrode ion trap is highly promising for practical quantum computing due to its superior controllability on the trapped ions. With advanced microfabrication techniques, silicon has been developed as an ion trap substrate for delicate surface electrodes design and monolithic electro-optical components integration. However, the high RF loss of silicon hinders the possible large-scale implementation. In this work, we demonstrate a through silicon via (TSV) integrated ion trap, which has low RF loss due to the elimination of wire bonding (WB) pads on the surface and the miniaturization of form factor. We also fabricate two types of conventional WB traps with or without a grounding screen layer. The RF performances of different ion traps are tested and compared, in terms of on-chip S-parameter, postpackaging resonance, and resulting power loss. The results show that the TSV trap has low S21 (~0.2 dB at 50 MHz), highQfactor (~22), and low power loss (0.26 W) compared to WB traps. In addition, 3-D finite element modeling (FEM) is employed for electric field visualization and RF loss analysis of different traps. The extracted results from the modeling show a decent agreement with the measurements. In addition to various RF tests, the design, fabrication, and ion trapping operation of different ion traps are presented. This work provides insights into RF loss of ion trapping devices and offers a new solution for RF loss reduction.
The surface-electrode ion trap is one of the key devices in modern ion-trapping apparatus to host the ion qubits for quantum computing. Surface traps fabricated on the silicon substrate have the versatility for complex electrode fabrication with 3-D integration capability. However, Si-induced dielectric loss has to be considered in trap design, and a ground structure is being incorporated to mitigate this concern. In this article, surface-electrode ion trap is fabricated using the standard Cu back-end process on a 300-mm Si wafer platform. Several process novelties are demonstrated: 1) the use of electroplated Cu/Au layers using microfabrication techniques to form the surface electrodes; 2) the use of dry etching to form the fine-gap oxide trench between the electrodes for reducing the charge-induced stray electric field; 3) the use of Cu mesh ground structure to enhance the resonance performance of the trap; and 4) process optimization to minimize the undercut in Cu/Au electrodes. Promising electrical properties are obtained from the fabricated ion trap with a leakage current failure rate of40μmare evaluated for their resonance performance with and without the ground plane. By incorporating ground plane into the ion trap, the resonance performances are significantly improved with an output power increment of 11 and 13 dB andQfactor increment of 2 and 6 for the corresponding trap types.