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A LDPC Parity Check Matrix Construction for Parallel Hardware Decoding

François S. Verdier, David Declercq

Published Sep 1, 2003• 10 citations
OpenAlex

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A method for constructing low-density parity-check (LDPC)code that can be implemented with high speed parallel decoding structure is proposed.Firstly,aparity-check matrix is generated with algebraic method.The short circles in the matrix can be eliminated by selecting proper parameters,so that the generated code has good performance.Then rearrange the rows of the generated parity-check matrix with specific rules to make the rearranged matrix has block structure.With the block structure,the partial parallel decoding of LDPC code can be realized in engineering,and a lot of resources can be saved.The simulation results show that the performance of constructed LDPC code is also very good and is equal to the random code.

Transactions of Beijing Institute of Technology•Jan 1, 2010•0 citations
In this paper, we construct the cyclic block-type low-density parity-check (CB-LDPC) codes for low complexity hardware implementation. The CB-LDPC code, which is a special class of quasi-cyclic LDPC (QC-LDPC), has an efficient encoding algorithm due to the simple structure of their parity-check matrices. A distribution of irregular parity-check matrix for the CB-LDPC is developed so that we can obtain an area-efficient decoder design, good error correction performance, and low complexity architecture implementation. The CB-LDPC code decoding uses the iterative min-sum algorithm (MSA) and the block parallel connection design to improve the hardware architecture complexity and area.
This paper presents a construction for low and high rate Low-Density Parity Check (LDPC) codes, their performance and efficient hardware implementation. The problem with decoding for LDPC codes is the linear increase in resource requirements as the size of the parity check matrix increases. This results in a number of issues with regard to practical implementation. These issues include interconnect routing, memory size and parallelism. A construction for low complexity, variable rate LDPC code will be introduced and an architecture that takes advantage of certain properties of this construction is proposed. A versatile LDPC decoding architecture is then evaluated on FPGA.
A method for constructing low-density parity-check (LDPC)code that can be implemented with high speed parallel decoding structure is proposed.Firstly,aparity-check matrix is generated with algebraic method.The short circles in the matrix can be eliminated by selecting proper parameters,so that the generated code has good performance.Then rearrange the rows of the generated parity-check matrix with specific rules to make the rearranged matrix has block structure.With the block structure,the partial parallel decoding of LDPC code can be realized in engineering,and a lot of resources can be saved.The simulation results show that the performance of constructed LDPC code is also very good and is equal to the random code.