Investigations on certain LDPC decoding algorithms for efficient hardware implementation

Lei Shi

A novel Low-Density Parity-Check(LDPC) decoding algorithm was proposed,which integrates the serial belief propagation mechanism with the normalized BP-Based updating rule.The algorithm propagates the belief according to certain order of the check nodes,thus improves the convergence property of the belief propagation.Meanwhile,the algorithm efficiently lowers the decoding complexity by using the normalized BP-Based updating rule,which makes the algorithm to adapt to the implementation of hardware.Simulation was performed under the AWGN channel and results show that,compared with prior LDPC decoding algorithm,the proposed algorithm is able to accelerate the convergence speed of decoding obviously and enhance the decoding performance significantly.

Emmanuel Boutillon

Mong‐Kai Ku, Huan-Sheng Li, Yi-Hsing Chien

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Emmanuel Boutillon

Ting Lin, Shan Cecilia Cao, Shunqing Zhang +2 more

With the raised requirements by 5G wireless communications, a reconfigurable decoder supporting both LDPC codes (for data plane) and polar codes (for control plane) is required. Due to the inherent structure differences between LDPC codes and polar codes, an straightforward combination of existing decoders is generally difficult. In this paper, we propose a joint decoding algorithm by analyzing the standard-compatible coding structure and re-investigating the merged BP algorithm. Based on that, we implement the joint decoding scheme using a pipelined hardware architecture and show that the proposed approach achieves higher hardware efficiency than traditional schemes. Decoding performance loss is negligible if compared with existing stand-alone LDPC or polar decoder.

Amrit Pal Singh, Sanjay Sharma