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IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

A Reconfigurable Decoder for Standard-Compatible LDPC Codes and Polar Codes

Ting Lin, Shan Cecilia Cao, Shunqing Zhang, Shugong Xu, Chuan Zhang

Published Nov 1, 2019• 4 citations
Publisher

Abstract

With the raised requirements by 5G wireless communications, a reconfigurable decoder supporting both LDPC codes (for data plane) and polar codes (for control plane) is required. Due to the inherent structure differences between LDPC codes and polar codes, an straightforward combination of existing decoders is generally difficult. In this paper, we propose a joint decoding algorithm by analyzing the standard-compatible coding structure and re-investigating the merged BP algorithm. Based on that, we implement the joint decoding scheme using a pipelined hardware architecture and show that the proposed approach achieves higher hardware efficiency than traditional schemes. Decoding performance loss is negligible if compared with existing stand-alone LDPC or polar decoder.

DOI
10.1109/apccas47518.2019.8953182

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With the raised requirements by 5G wireless communications, a reconfigurable decoder supporting both LDPC codes (for data plane) and polar codes (for control plane) is required. Due to the inherent structure differences between LDPC codes and polar codes, an straightforward combination of existing decoders is generally difficult. In this paper, we propose a joint decoding algorithm by analyzing the standard-compatible coding structure and re-investigating the merged BP algorithm. Based on that, we implement the joint decoding scheme using a pipelined hardware architecture and show that the proposed approach achieves higher hardware efficiency than traditional schemes. Decoding performance loss is negligible if compared with existing stand-alone LDPC or polar decoder.
Recently, both polar codes and low-density parity-check (LDPC) codes have been adopted by 3GPP eMBB scenario. Since both codes exist in one system, it is natural to consider the concatenation scheme of them. In this paper, a merged belief propagation (BP) decoding algorithm for the concatenated codes of polar and LDPC codes is proposed. By jointing factor graphs, this merged algorithm is designed by serially executing the LDPC and polar decoding. According to numerical results, the bit error rate (BER) of this proposed algorithm can achieve a notable improvement for different code rates compared with the conventional separated approach. For (1024, 512) polar code, the performance gain of the proposed scheme is at least 0 5 dB even at a low BER of 1 × 10-2. Finally, further refinements of computational complexity and hardware implementation are also provided in this paper.
In the 5G communication systems, a hybrid approach to support polar codes for control plane and LDPC codes for data plane has been identified as the channel coding solution for enhanced mobile broadband (eMBB) scenario. One of the major challenges to implement this approach is to design powerful decoders at the terminal side. Inspired from a useful machine learning based polar decoder, we proposed a deep learning based unified polar-LDPC by concatenating an indicator section. Through numerical experiments, we show that the proposed deep neural network (DNN) based decoding architecture can achieve the similar decoding performance compared with the traditional BP-based decoding algorithm. Meanwhile, the proposed unified approach shares the same network architecture and parameters with isolated approaches, which saves significant implementation resources consequently.
In recent years, the amount of digital data which is stored and transmitted for private and public usage has increased considerably. To allow a save transmission and storage of data despite of error-prone transmission media, error correcting codes are used. A large variety of codes has been developed, and in the past decade low-density parity-check (LDPC) codes which have an excellent error correction performance became more and more popular. Today, low-density parity-check codes have been adopted for several standards, and efficient decoder hardware architectures are known for the chosen structured codes. However, the existing decoder designs lack flexibility as only few structured codes can be decoded with one decoder chip. In consequence, different codes require a redesign of the decoder, and few solutions exist for decoding of codes which are not quasi-cyclic or which are unstructured. In this thesis, three different approaches are presented for the implementation of fully programmable LDPC decoders which can decode arbitrary LDPC codes. As a design study, the first programmable decoder which uses a heuristic mapping algorithm is realized on a field-programmable gate array (FPGA), and error correction curves are measured to verify the correct functionality. The main contribution of this thesis lies in the development of the second and the third architecture and an appropriate mapping algorithm. The proposed fully programmable decoder architectures use one-phase message passing and layered decoding and can decode arbitrary LDPC codes using an optimum mapping and scheduling algorithm. The presented programmable architectures are in fact generalized decoder architectures from which the known decoder architectures for structured LDPC codes can be derived.
This paper presents a general decoder architecture for 5G LDPC and polar codes. To achieve the hardware reuse maximization, both LDPC and polar codes are decoded by belief propagation (BP) algorithm on sparse bipartite graphs. However, by counting the number of short cycles on the polar bipartite graphs, we observe that numerous short cycles cause the poor performance than conventional decoding algorithms, like successive cancellation (SC) and BP decoding. To reduce the impact of short cycles, a LDPC-like BP list (BPL) decoding algorithm is proposed for polar codes, which is applied on L different polar bipartite graphs constructed by different permuted polar factor graphs. Finally, the simulation shows that the proposed general decoder for polar codes can obtain beyond SC and BP error performance with lower decoding latency and computational complexity, and even near successive cancellation list (SCL) performance in high signal-noise ratios (SNRs).
The new 5G communications standard increases data rates and supports low-latency communication that places constraints on the computational complexity of channel decoders. 5G low-density parity-check (LDPC) codes have the so-called protograph-based raptor-like (PBRL) structure which offers inherent rate-compatibility and excellent performance. Practical LDPC decoder implementations use message-passing decoding with finite precision, which becomes coarse as complexity is more severely constrained. Performance degrades as the precision becomes more coarse. Recently, the information bottleneck (IB) method was used to design mutual-information-maximizing lookup tables that replace conventional finite-precision node computations. The IB approach exchanges messages represented by integers with very small bit width. This paper extends the IB principle to the flexible class of PBRL LDPC codes as standardized in 5G. The extensions include puncturing and rate-compatible IB decoder design. As an example of the new approach, a 4-bit information bottleneck decoder is evaluated for PBRL LDPC codes over a typical range of rates. Frame error rate simulations show that the proposed scheme outperforms offset min-sum decoding algorithms and operates very close to double-precision sum-product belief propagation decoding.
Abstract A hardware architecture is presented to decode (N, K) polar codes based on a low‐density parity‐check code‐like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single‐stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short‐to‐intermediate code lengths was implemented using the Virtex‐7 field‐programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast‐simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10−4 at 2.7 Eb/No (dB). It converged faster than the BP decoding scheme on a dense parity‐check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra‐scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error‐correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.