Some aspects of hardware implementation of LDPC codes

Emmanuel Boutillon

Mong‐Kai Ku, Huan-Sheng Li, Yi-Hsing Chien

Low-density parity-check (LDPC) codes have been widely considered as error-correcting codes for next generation communication systems. A good LDPC decoder design requires both implementation friendly LDPC codes and efficient decoder architectures. The quality of LDPC code is crucial in determining the coding gain and implementation complexity of LDPC hardware decoders. This paper presented a genetic algorithm (GA) based LDPC code search algorithm with hardware considerations. Regular quasi-cyclic LDPC codes are used due to its friendliness to hardware implementation. Our hardware architecture design schedules pipeline LDPC decoding operation to boost the hardware utilization efficiency (HUE) of LDPC decoder. A LDPC decoder with a block size of 12288 is implemented in FPGA to validate our code and architecture design.

Michaelraj Kingston Roberts

Baihong, Lin -, Yukui +5 more

Nheu, Christopher

\n \t\t\tAll digitally transmitted message signals suffer from noise. Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes are a family of structured LDPC codes that are capable of high performance error correcting capabilities. The aim of this thesis is to design a QC-LDPC code to correct messages passed through the binary erasure channel (BEC). The BEC is a channel model in which bits received correctly are known, or are unknown if received incorrectly.All types of LDPC codes are sparse matrices of many 0s and very few 1s. The placement of these 1s determines how well a code can correct errors. In theory, 1s can be placed in any configuration that gives high error correcting performance. However, this will likely come at the cost of complex hardware implementation. To compensate for this trade-off, QC-LDPC codes follow a specific structure in the placement of 1s to make the hardware implementation more efficient.In this thesis, a literature review of QC-LDPC codes is undertaken, codes are then designed and their performance verified by simulation on MATLAB. It also aims to implement QC-LDPC codes in hardware using the hardware description language VHDL. Testing of the hardware implementation is carried out by hardware simulation using the ModelSim software. The results of the software simulations shows that well designed QC- LDPC codes with girth of at least 6 are close to 0.1 from the Shannon Limit in the BEC. The hardware simulation expresses that decoding erasures from the BEC can occur rapidly in the range of megabits per second, which is significantly quicker than software simulations. It also demonstrates that the implementation of QC-LDPC codes in hardware have linear complexity proportional to the length of the message blocks of the code\n

Hao Zhong, Tong Zhang

This paper presents a design approach for low-density parity-check (LDPC) coding system hardware implementation by jointly conceiving irregular LDPC code construction and VLSI implementations of encoder and decoder. The key idea is to construct good irregular LDPC codes subject to two constraints that ensure the effective LDPC encoder and decoder hardware implementations. We propose a heuristic algorithm to construct such implementation-aware irregular LDPC codes that can achieve very good error correction performance. The encoder and decoder hardware architectures are correspondingly presented.