\n \t\t\tAll digitally transmitted message signals suffer from noise. Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes are a family of structured LDPC codes that are capable of high performance error correcting capabilities. The aim of this thesis is to design a QC-LDPC code to correct messages passed through the binary erasure channel (BEC). The BEC is a channel model in which bits received correctly are known, or are unknown if received incorrectly.All types of LDPC codes are sparse matrices of many 0s and very few 1s. The placement of these 1s determines how well a code can correct errors. In theory, 1s can be placed in any configuration that gives high error correcting performance. However, this will likely come at the cost of complex hardware implementation. To compensate for this trade-off, QC-LDPC codes follow a specific structure in the placement of 1s to make the hardware implementation more efficient.In this thesis, a literature review of QC-LDPC codes is undertaken, codes are then designed and their performance verified by simulation on MATLAB. It also aims to implement QC-LDPC codes in hardware using the hardware description language VHDL. Testing of the hardware implementation is carried out by hardware simulation using the ModelSim software. The results of the software simulations shows that well designed QC- LDPC codes with girth of at least 6 are close to 0.1 from the Shannon Limit in the BEC. The hardware simulation expresses that decoding erasures from the BEC can occur rapidly in the range of megabits per second, which is significantly quicker than software simulations. It also demonstrates that the implementation of QC-LDPC codes in hardware have linear complexity proportional to the length of the message blocks of the code\n
\n \t\t\tAll digitally transmitted message signals suffer from noise. Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes are a family of structured LDPC codes that are capable of high performance error correcting capabilities. The aim of this thesis is to design a QC-LDPC code to correct messages passed through the binary erasure channel (BEC). The BEC is a channel model in which bits received correctly are known, or are unknown if received incorrectly.All types of LDPC codes are sparse matrices of many 0s and very few 1s. The placement of these 1s determines how well a code can correct errors. In theory, 1s can be placed in any configuration that gives high error correcting performance. However, this will likely come at the cost of complex hardware implementation. To compensate for this trade-off, QC-LDPC codes follow a specific structure in the placement of 1s to make the hardware implementation more efficient.In this thesis, a literature review of QC-LDPC codes is undertaken, codes are then designed and their performance verified by simulation on MATLAB. It also aims to implement QC-LDPC codes in hardware using the hardware description language VHDL. Testing of the hardware implementation is carried out by hardware simulation using the ModelSim software. The results of the software simulations shows that well designed QC- LDPC codes with girth of at least 6 are close to 0.1 from the Shannon Limit in the BEC. The hardware simulation expresses that decoding erasures from the BEC can occur rapidly in the range of megabits per second, which is significantly quicker than software simulations. It also demonstrates that the implementation of QC-LDPC codes in hardware have linear complexity proportional to the length of the message blocks of the code\n
There is an important breakthrough in the field of forward error correction techniques, low-density parity-check (LDPC) codes. These codes have potential to approach the Shannon limit with reliable performance on a given channel, known as the channel capacity. Recently, researchers pay much more attention towards LDPC codes because its performance is better than Turbo codes. However, the LDPC code is the best when it is an irregular code and uses with a very large block-length. Although, the short block-length LDPC codes perform not so well, they are easy to implement in various practical applications. Therefore, there is still a demand of new development on the encoding side of LDPC codes for various ranges of code rate and code length so as to capable of using in many applications.This thesis proposes the development of quasi-cyclic (QC) LDPC codes for column weight 3. In the first part of this thesis, we propose a new construction algorithm of QC-LDPC codes for medium to large block-length by combining QC-LDPC codes of small block-length as their component codes, via Chinese remainder theorem (CRT). Such component codes were constructed by permuting each column block sequentially to attain the desire local girth. After combining all component codes to generate an expanded parity-check matrix, the resulting girth is greater than or at least equal to the maximum girth of the component codes. Simulation results show that our proposed construction method of the parity-check matrix significantly outperforms the other well-known existing methods in terms of low error-floor, simple structure, high performance, and can reduce encoding complexity.In addition, this thesis also proposes two new construction methods for QC-LDPC codes, namely a base matrix method and a subtraction based method. A base matrix based method is a simple, less computational complexity method for constructing the exponent matrix (3, K) of girth 8, 10 and 12 of QC-LDPC codes. Another method is a subtraction method, which has a similar exponent matrix as a base matrix method and has a girth at least 8. Results indicate that the LDPC codes constructed from these two methods have flexibility for arbitrary block-column length K and have a similar BER performance if compared to existing methods.
Low-density parity-check (LDPC) codes have been one of the most popular error correction candidates in modern communication and data storage systems for the past three decades due to their capacity-approaching error correction capability under the Belief Propagation (BP) decoding algorithms. In this dissertation, we investigate three topics related to efficient and effective decoding algorithms and the code design of LDPC codes. In the first part of this dissertation, we propose a methodology with the help of artificial intelligence to design Finite Alphabet Iterative Decoders (FAID) for LDPC codes, which are not only of great theoretical but also practical importance. This model-driven neural network (NN) framework unfolds the decoding iterations, introduces quantized neural networks (QNN) to model the FAIDs, and proposes a new cost function, namely, bit error rate (BER), to address the inefficiency in discrete-output channel scenarios. The low precision activations in the QNN and quantization in the cost functions cause a critical issue that their gradients vanish almost everywhere, making it difficult to use classical backward propagation. We design and leverage straight-through estimators as surrogate gradients to tackle this issue and provide a joint training scheme. These QNN-aided FAIDs, are capable of surpassing the floating-point BP algorithms, with much lower complexity and faster convergence. The QNN-aided approach is general, as it can be applied to both continuous and discrete-output channels. In the second part of this dissertation, we propose a new code construction of LDPC codes based on the conventional parity-check matrices of Reed-Solomon (RS) codes. We investigate the girth and cycle structure and introduce an efficient searching algorithm to reduce short cycles in their Tanner graphs and to construct LDPC codes with a girth of at least eight. We use masking to further reduce the number of short cycles and to adjust the column and row weights of the parity-check matrices of the constructed codes for performance improvement. Our designs are systematic and flexible, which balance the requirements of good waterfall performance and low error-floor while maintaining a structure that facilitates implementation. In the third part of this dissertation, we investigate binary quasi-cyclic (QC) LDPC codes and their capability to correct phased bursts of erasures. We prove that the peeling algorithm when applied to such parity-check matrices of column weight two can correct all erasures that can be corrected by a maximum likelihood (ML) decoder. We show that by modifying the parity-check matrices of column weight two and globally coupling them, the erasure correcting capability can be further enhanced. For the Additive White Gaussian Noise (AWGN) channel, we design QC LDPC codes with parity-check matrices of column weight three or more that can correct phased bursts of erasures and perform well over the AWGN channel. Our analysis of QC-LDPC codes with parity-check matrices of column weight two is rather comprehensive as we determine, for all such codes, their dimensions, minimum Hamming distances, and their capabilities to correct phased bursts.
Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family
In this paper, we propose a simple mathematical structure to improve the BER (bit error rate) performance of quasi-cyclic low-density parity-check (QC-LDPC) codes. Since the proposed structure can be defined in-between those of random codes and structured codes, these proposed QC-LDPC codes not only perform as well as random-LDPC codes, but also preserve the advantage of structured LDPC codes which is easier to implement over coding hardware. Moreover, the proposed structure, constructed from balanced incomplete block design (BIBD), can reduce the density of parity-check matrix and hence reduce the number of short cycles, which generally lead to better performance. At the end, we show that the error floor performance of QC-LDPC codes can be improved by proposed hybrid structures and perform well over binary-input additive white Gaussian noise (BI-AWGN) channel.
Low-Density Parity-Check (LDPC) codes are among the most effective modern error-correcting codes due to their excellent correction performance and highly parallel decoding scheme. Moreover, the nonbinary extension of such codes further increases performance in the short-block regime. In this paper, we review the key elements for the construction of implementation-oriented binary and nonbinary codes. These Quasi-Cyclic LDPC (QC-LDPC) codes additionally feature efficient encoder and decoder implementation frameworks. We then present a versatile algorithm for the construction of both binary and nonbinary QC-LDPC codes that have low encoding complexity and an optimized corresponding graph structure. Our algorithm uses a progressive edge growth algorithm, modified for QC-LDPC graph construction, and then performs an iterative global search for optimized cyclic shift values within the QC-LDPC circulants. Strong error correction performance is achieved by minimizing the number of short cycles, and cycles with low external connectivity, within the code graph. We validate this approach via error rate simulations of a transmission system model featuring an LDPC coder-decoder, digital modulation, and additive white Gaussian noise channels. The obtained numerical results validate the effectiveness of the proposed construction algorithm, with a number of constructed codes exhibiting either similar or superior performance to industry standard binary codes and selected nonbinary codes from the literature.
The existing design of quasi-cyclic(QC) low-density parity-check(LDPC) codes has not considered the problems of short length girths and the rows' dependency.The first problem leads to the BER performance of QC LDPC codes to be much poorer than that of randomly constructed LDPC codes,while the second problem leads to the difficulty of construction of generator matrices from parity-check matrices.To solve the first problem,the constraint conditions for designing the QC LDPC codes are proposed,and the dimension and shift factors of the circulant matrices of the given sparse parity-check matrix are adjusted according to the test results of both girth 4 and girth 6.To solve the second problem,an approach of irregular QC LDPC codes is proposed.The proposed approach is to replace some sub-matrices by zero matrices and identity matrices at special positions in the given sparse parity-check matrix so as to get a nonsingular square matrix for the construction of the generator matrix.Though adopting bidiagonal submatrices in parity-check matrix can solve the rows' dependency problem,many code words with low weights will occur,which leads to the BER performance can not be better by increasing code lengths.Examples are provided for the proposed design of QC LDPC codes,and computer simulation results show that the proposed QC LDPC codes achieve good BER performance.