Parallel LDPC Decoding

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

M. Vijay, K. Mohaneswari

This paper aims to develop a serial and parallel Projective geometric LDPC decoder. The Low-Density Parity-Check codes are among the most powerful forward error correcting codes. LDPC codes are recently used for many high bandwidth applications. A parallel decoding scheme is also proposed to shorten the decoding time. Parallel architecture is employed here to increase the throughput. The proposed decoder is verified through simulation and the results are presented. In this work, Xilinx/Modelsim simulations of the serial and parallel Projective geometric LDPC decoder have been performed With the (7, 3) PG-LDPC code, the implemented parallel decoder requires less decoding time than the serial decoder.

Valentin Savin

Kazumi Shimizu, Tatsuyuki Ishikawa, Nozomu Togawa +2 more

This paper proposes a partially-parallel LDPC decoder based on a high-efficiency message-passing algorithm. Our proposed partially-parallel LDPC decoder performs the column operations for bit nodes in conjunction with the row operations for check nodes. Bit functional unit with pipeline architecture in our LDPC decoder allows us to perform column operations for every bit node connected to each of check nodes which are updated by the row operations in parallel. Our proposed LDPC decoder improves the tuning when the column operations are performed, accordingly it improves the message-passing efficiency within the limited number of iterations for decoding. We implemented the proposed partially-parallel LDPC decoder on an FPGA, and simulated its decoding performance. Practical simulation shows that our proposed LDPC decoder reduces the number of iterations for decoding, and it improves the bit error performance with a small hardware overhead.

Hua Xu, Wei Wan, Wei Wang +3 more

Low-Density Parity-Check (LDPC) codes are powerful error correcting codes. LDPC decoders have been implemented as efficient error correction codes on dedicated VLSI hardware architectures in recent years. This paper describes two strategies to parallelize min-sum decoding of irregular LDPC codes. The first implements min-sum LDPC decoders on multicore platforms using OpenMP, while the other uses the Compute Unified Device Architecture (CUDA) to parallelize LDPC decoding on Graphics Processing Units (GPUs). Empirical studies on data with various scales show that the performance of these decoding processes is improved by these parallel strategies and the GPUs provide more efficient, fast implementation decoder.

Neethu Yesudas, Abhishek Anand