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Elsevier eBooks

LDPC Decoders

Valentin Savin

Published Jan 1, 2014• 12 citations
Publisher
DOI
10.1016/b978-0-12-396499-1.00004-2

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Stochastic decoding for LDPC convolutional codes

Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang +1 more

Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.

IEEE International Symposium on Circuits and Systems proceedings•May 1, 2012•3 citations

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Recently, the concept of layered decoding schedule for Low-Density Parity-Check codes has been introduced. But the advantage of layered decoding schedule for irregular LDPC codes is not as obvious as regular LDPC codes. The major drawback of the layered irregular LDPC codes versus the layered regular LDPC codes is its comparative low convergence decoding speed. Simulation results show that different bit node degrees of irregular LDPC codes significantly contribute to the decoding performance. The decoding performance of bit nodes with different degrees is of great difference. Bit nodes with small degrees always converge slower than larger ones. In this paper, we propose an optimized decoding schedule for irregular LDPC codes to accelerate the decoding convergence rate. Meanwhile, for the irregular LDPC decoder, the faster decoding speed means a higher throughput and almost the same error performance.

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The article introduces a new LDPC decoding algorithm based on Equivalent Parity Check Matrix. Simulation results show that the new LDPC decoding algorithm can improve LDPC decoding performance. Compared to some other improvements, the new LDPC decoding algorithm, which is simpler, can detect errors and be applied to LDPC codes for great-length LDPC codes.

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LDPC decoding algorithms

Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz

Elsevier eBooks•Dec 12, 2017•2 citations
Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.
Recently, the concept of layered decoding schedule for Low-Density Parity-Check codes has been introduced. But the advantage of layered decoding schedule for irregular LDPC codes is not as obvious as regular LDPC codes. The major drawback of the layered irregular LDPC codes versus the layered regular LDPC codes is its comparative low convergence decoding speed. Simulation results show that different bit node degrees of irregular LDPC codes significantly contribute to the decoding performance. The decoding performance of bit nodes with different degrees is of great difference. Bit nodes with small degrees always converge slower than larger ones. In this paper, we propose an optimized decoding schedule for irregular LDPC codes to accelerate the decoding convergence rate. Meanwhile, for the irregular LDPC decoder, the faster decoding speed means a higher throughput and almost the same error performance.