Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE International Symposium on Circuits and Systems proceedings

Stochastic decoding for LDPC convolutional codes

Xin-Ru Lee, Chih-Lung Chen, Hsie-Chia Chang, Chen‐Yi Lee

Published May 1, 2012• 3 citations
Publisher

Abstract

Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.

DOI
10.1109/iscas.2012.6271843

Related papers

Enhancing the Decoding of Short LDPC Codes with Stochastic Sequences

Yuyuan Gu, Haien Li

Low-Density Parity-Check (LDPC) codes are one of the most popular codes used in nowadays’ communication due to their high coding efficiency at low decoding complexity. With these characteristics, LDPC codes are suitable for high-speed information transmission systems. The widely used decoding algorithm for LDPC codes is Belief Propagation (BP) decoding with which the performance of LDPC codes can approach the Shannon limit. With the development of 5G, a lot of attention is given to the so-called ultra-reliable low latency communication scenario which needs the short code to transmit. However, short codes will not have a very good performance with BP decoding. To solve this problem, investigations have been done such as multiple-bases BP decoding. Although this decoding method has a better performance than BP decoding, it will cause a high complexity in the hardware implementation. Besides, an investigation on the stochastic decoding for shortcodes was proposed in 2003. This decoding method is hardware friendly, but its performance can only approach BP decoding. Inspired by multiple-bases BP decoding and stochastic decoding, binary stochastic decoding with parallel decoders is proposed in this thesis firstly. It represents stochastic sequences with multiple parallel Tanner graphs and uses hard-decision decoding in the iterative part because of the binary input bits. However, this decoding method has a severe performance loss compared to BP decoding. To avoid this problem, the enhancement method is used to make the binary sequences be non-binary sequences that can form more powerful parallel decoders. Then the non-binary symbols of these new sequences are transformed to their corresponding log-likelihood ratio which enables the iterative part to use BP decoding. In addition, combining with the ML decision of list decoding, the decision part of our stochastic decoder can fully utilize the output to increase the efficiency of the decoding method. After ensuring the performance of our non-binary stochastic decoding to be better than BP decoding, the complexity of the decoder is reduced to save the computational resources. Finally, with constant adjustments, the bit width of each non-binary symbol is determined to be 15, and the sequence length is reduced to 20 which can let the non-binary stochastic decoding has an acceptable complexity while keeping good performance.

•Jan 1, 2021•1 citation

CNN-Based Approach for Enhancing 5G LDPC Code Decoding Performance

Sivarama Prasad Tera, Ravikumar Chinthaginjala, Priya Natha +3 more

This paper presents the novel Stochastic decoding-convolutional neural network (SD-CNN) structure, with the goal of enhancing 5G LDPC code’s decoding efficiency in the presence of correlated noise of the channel. Applying the stochastic approach acts as an alternate technique to fixed-point LDPC decoding to enhance the decoder’s hardware efficiency. In order to improve the efficacy of the decoder, we adopted deep learning method such as Convolutional neural network (CNN). CNNs can be employed for denoising purposes in communication systems, where signals may be compromised by diverse forms of noise while being transmitted, with the aim of enhancing signal quality and dependability. The SD-CNN architecture combines a trained CNN with a stochastic decoder of 5G LDPC codes, thereby utilizing the CNN’s capability to accurately estimate channel noise and, consequently, enhance the error correction capabilities of the decoder. The generated output of the trained CNN is then fed back into the stochastic decoder, creating an iterative process between the SD and CNN that ultimately leads to superior decoding performance. For 5G LDPC code word length$N = 3808$, with a base code rate$R = 1/3$, the suggested SD-CNN architecture achieves a BER of$10^{-6}$at 0.6 dB of SNR per bit in the strong correlation of channel noise condition, in comparison to SD, which achieves a BER of$10^{-6}$at 3.5 dB of SNR per bit. The results demonstrate that there is a 2.9 dB improvement.

IEEE Access•Jan 1, 2024•28 citations

Controlled start-up stochastic decoding of LDPC codes

Mountassar Maamoun, Rafik Bradai, Ali Naderi +2 more

This paper concerns a new and powerful Low-Density Parity-Check (LDPC) stochastic decoding algorithm, called Controlled Start-up Stochastic (CSS) decoding, to implement fully parallel LDPC decoders. The proposed algorithm uses a clever starting point computing method to improve the convergence as well as to reduce the latency of the decoding process, without a significant hardware complexity cost. Using this stochastic method, in low signal-to-noise ratio (SNR) region, a short LDPC code can outperforms the fixed point state-of-the-art (2048, 1723) LDPC code. To validate the performance of the proposed algorithm, a (48, 24) LDPC code are implemented on Xilinx Virtex-6 VLX240T field programmable gate array device, with and without the CSS method. The new algorithm provides a decoding speed seven times faster and a Bit Error Rate (BER) hundred times better at E3/N0=4.5 dB. In addition, the results provide a BER better than the 6 bits offset min-sum algorithm (OMSA) and better than the 6 bits sum-product algorithm (SPA) for the (2048, 1723) LDPC code, below E3/N0=3.9 dB and Eb/N0=4.3 dB respectively. The obtained results show that, the proposed algorithm is the first stochastic algorithm which can outperform the OMSA and SPA algorithms, with less hardware complexity.

IEEE International New Circuits and Systems Conference (NEWCAS)•Jun 1, 2013•6 citations

Dynamic Window Decoding for LDPC Convolutional Codes in Low-Latency Optical Communications

Tian Xia, Toshiaki Koike–Akino, David S. Millar +5 more

We propose a dynamic window decoding scheme for LDPC convolutional codes to reduce the latency compared to the belief propagation decoding. The BER performance of our proposed memory-efficient decoding scheme is verified by simulations.

Optical Fiber Communication Conference•Jan 1, 2015•3 citations

Design of an Iteration-Reduced LDPC-CC Decoder Based on Compact Decoding Architecture

Liangxi Liu, Ming Zhan, Mingjuan Qiu +3 more

In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10-4and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.

Annual Conference of the IEEE Industrial Electronics Society (IECON)•Oct 18, 2020•0 citations

Design and analysis of stochastic 5G new radio LDPC decoder using adaptive sparse quantization kernel least mean square algorithm for optical satellite communications

R. Krishna Priya, Nitin Nandkumar Sakhare, Ajay Namdeorao Paithane +2 more

Abstract A Stochastic Low‐Density Parity‐Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal‐to‐noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC‐ASQ‐KLMSA), this paper proposes an area‐efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE‐T standard and used in this study. We examine the ASQ‐KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter‐connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ‐KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub‐node of the degree‐6 VN was changed with an adder‐based 5–1 input grouping sub‐node for the (2048, 1723) code in order to get more accurate results when the check‐to‐variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC‐ASQ‐KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher‐performance stochastic LDPC decoder architecture designed through correlation analysis (HP‐SLDPC‐CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit‐Serial Stochastic Updating(HLDPC‐BSSU), Flexible FPGA‐Based Stochastic Decoder for 5G LDPC codes (FPGA‐SD‐5G‐LDPC), respectively.

Internet Technology Letters•May 19, 2024•1 citation
Among LDPC codes, LDPC convolutional codes (LDPC-CCs) seem to be more suitable for variable length applications. However, a LDPC-CC decoder is difficult to implement for its long latency and large storage usage. The stochastic computation makes the decoding of LDPC-CCs more efficient, but the boundary effect of sliding window causes poor performance. In this paper, a stochastic LDPC-CC decoder with virtual edge compensation as well as decoder architecture is presented. The simulation results based on (491, 3, 6) time-varying LDPC-CC show that under the same signal-to-noise ratio, our proposed decoder could achieve better performance, 60% less decoding latency and 40% storage reduction compared to log-BP decoder with 10 processors.
Low-Density Parity-Check (LDPC) codes are one of the most popular codes used in nowadays’ communication due to their high coding efficiency at low decoding complexity. With these characteristics, LDPC codes are suitable for high-speed information transmission systems. The widely used decoding algorithm for LDPC codes is Belief Propagation (BP) decoding with which the performance of LDPC codes can approach the Shannon limit. With the development of 5G, a lot of attention is given to the so-called ultra-reliable low latency communication scenario which needs the short code to transmit. However, short codes will not have a very good performance with BP decoding. To solve this problem, investigations have been done such as multiple-bases BP decoding. Although this decoding method has a better performance than BP decoding, it will cause a high complexity in the hardware implementation. Besides, an investigation on the stochastic decoding for shortcodes was proposed in 2003. This decoding method is hardware friendly, but its performance can only approach BP decoding. Inspired by multiple-bases BP decoding and stochastic decoding, binary stochastic decoding with parallel decoders is proposed in this thesis firstly. It represents stochastic sequences with multiple parallel Tanner graphs and uses hard-decision decoding in the iterative part because of the binary input bits. However, this decoding method has a severe performance loss compared to BP decoding. To avoid this problem, the enhancement method is used to make the binary sequences be non-binary sequences that can form more powerful parallel decoders. Then the non-binary symbols of these new sequences are transformed to their corresponding log-likelihood ratio which enables the iterative part to use BP decoding. In addition, combining with the ML decision of list decoding, the decision part of our stochastic decoder can fully utilize the output to increase the efficiency of the decoding method. After ensuring the performance of our non-binary stochastic decoding to be better than BP decoding, the complexity of the decoder is reduced to save the computational resources. Finally, with constant adjustments, the bit width of each non-binary symbol is determined to be 15, and the sequence length is reduced to 20 which can let the non-binary stochastic decoding has an acceptable complexity while keeping good performance.
This paper presents the novel Stochastic decoding-convolutional neural network (SD-CNN) structure, with the goal of enhancing 5G LDPC code’s decoding efficiency in the presence of correlated noise of the channel. Applying the stochastic approach acts as an alternate technique to fixed-point LDPC decoding to enhance the decoder’s hardware efficiency. In order to improve the efficacy of the decoder, we adopted deep learning method such as Convolutional neural network (CNN). CNNs can be employed for denoising purposes in communication systems, where signals may be compromised by diverse forms of noise while being transmitted, with the aim of enhancing signal quality and dependability. The SD-CNN architecture combines a trained CNN with a stochastic decoder of 5G LDPC codes, thereby utilizing the CNN’s capability to accurately estimate channel noise and, consequently, enhance the error correction capabilities of the decoder. The generated output of the trained CNN is then fed back into the stochastic decoder, creating an iterative process between the SD and CNN that ultimately leads to superior decoding performance. For 5G LDPC code word lengthN=3808N = 3808N=3808, with a base code rateR=1/3R = 1/3R=1/3, the suggested SD-CNN architecture achieves a BER of10−610^{-6}10−6at 0.6 dB of SNR per bit in the strong correlation of channel noise condition, in comparison to SD, which achieves a BER of10−610^{-6}10−6at 3.5 dB of SNR per bit. The results demonstrate that there is a 2.9 dB improvement.
This paper concerns a new and powerful Low-Density Parity-Check (LDPC) stochastic decoding algorithm, called Controlled Start-up Stochastic (CSS) decoding, to implement fully parallel LDPC decoders. The proposed algorithm uses a clever starting point computing method to improve the convergence as well as to reduce the latency of the decoding process, without a significant hardware complexity cost. Using this stochastic method, in low signal-to-noise ratio (SNR) region, a short LDPC code can outperforms the fixed point state-of-the-art (2048, 1723) LDPC code. To validate the performance of the proposed algorithm, a (48, 24) LDPC code are implemented on Xilinx Virtex-6 VLX240T field programmable gate array device, with and without the CSS method. The new algorithm provides a decoding speed seven times faster and a Bit Error Rate (BER) hundred times better at E3/N0=4.5 dB. In addition, the results provide a BER better than the 6 bits offset min-sum algorithm (OMSA) and better than the 6 bits sum-product algorithm (SPA) for the (2048, 1723) LDPC code, below E3/N0=3.9 dB and Eb/N0=4.3 dB respectively. The obtained results show that, the proposed algorithm is the first stochastic algorithm which can outperform the OMSA and SPA algorithms, with less hardware complexity.
In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10-4and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.
Abstract A Stochastic Low‐Density Parity‐Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal‐to‐noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC‐ASQ‐KLMSA), this paper proposes an area‐efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE‐T standard and used in this study. We examine the ASQ‐KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter‐connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ‐KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub‐node of the degree‐6 VN was changed with an adder‐based 5–1 input grouping sub‐node for the (2048, 1723) code in order to get more accurate results when the check‐to‐variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC‐ASQ‐KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher‐performance stochastic LDPC decoder architecture designed through correlation analysis (HP‐SLDPC‐CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit‐Serial Stochastic Updating(HLDPC‐BSSU), Flexible FPGA‐Based Stochastic Decoder for 5G LDPC codes (FPGA‐SD‐5G‐LDPC), respectively.