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Annual Conference of the IEEE Industrial Electronics Society (IECON)

Design of an Iteration-Reduced LDPC-CC Decoder Based on Compact Decoding Architecture

Liangxi Liu, Ming Zhan, Mingjuan Qiu, Meng Wang, Xiaohong Luo, Jing Guo

Published Oct 18, 2020• 0 citations
Publisher

Abstract

In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10-4and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.

DOI
10.1109/iecon43393.2020.9254828

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In recent years, the demand for low latency and high reliability in industrial have been increasing rapidly. To meet these requirements, we propose a new decoding architecture of low-density parity-check convolutional codes (LDPC-CC). The proposed decoding architecture reduces the distance of the neighboring processors by using the rationale of compact pipeline decoder. At the same time, the stopping rule is employed in the process of iteration and the weighting factor is added to reduce the error propagation caused by the update of the parity-check node, thus accelerating the convergence of the decoding. The results show that the proposed algorithm has about 0.3 dB gain compared with the on-demand variable node activation (OVA) algorithm when the bit rate error (BER) is 10-4and maximum number of iterations is 10. Meanwhile, the initial delay and storage requirement are reduced by about 50% and the average number of iterations per decoded bit is also reduced largely.
A novel belief propagation(BP) decoding algorithm for convolutional low-density parity-check codes is proposed.The proposed algorithm raises the efficiency of updating the variable information by applying feedback information at each decoding iteration and employs the weighting factor to reduce the error propagation caused by the cycles in the Tanner graph,thus yielding a faster convergence of the decoding.Simulation results show that an error performance better than that of the existing belief propagation algorithm can be achieved,while the 5/8 decoding delay and the computation complexity are effectively reduced.Compared with the existing BP,the proposed algorithm achieves a gain of 0.16dB at the BER of 10-6 with the same number of iterations.
A feedback belief propagation (BP) decoding algorithm for low-density parity-check convolutional codes is proposed. The proposed algorithm can activate the variable nodes more efficiently by applying feedback decoding at each decoding iteration. Compared with the on-demand BP algorithm, the proposed algorithm has a doubled convergence speed and causes only about half of the decoding delay at similar error performances without any increase of storage requirement. Simulation results show that the proposed algorithm can offer a good trade-off between the error-correcting performance and the decoding complexity.
Nonbiliary low-density parity-check (LDPC) codes can lead to excellent error performance while the codewords are of short or moderate length. However, the high decoding complexity of nonbiliary LDPC codes inevitably depreciates their practical values. The computational bottleneck arises from the check node processing in the iterative message passing (MP) algorithms which terminate when either all parity checks are satisfied or the maximum iteration number is reached. We have observed that for undecodable blocks, the MP algorithms always run up to the maximum iteration limit and therefore cannot generate the correct codeword. Thus, it would be better to terminate the algorithms early so as to save the unnecessary computational time and reduce the extra power consumption when undecodable blocks are experienced. In this paper, we propose a new T-tolerance stopping criterion for LDPC decoders by exploiting the fact that the total a posteriori probability (APP) should increase as the iteration number grows. Simulation results demonstrate that our proposed new T-tolerance criterion can greatly reduce the average iteration number (complexity) while restricting the decoding performance degradation within 0.1 dB in low bit-energy-to-noise ratio scenarios.
Abstract: In this paper, a fast-convergence algorithm is proposed for the decoding of low-density parity-check (LDPC) codes. By putting more weight on the message update from check node to variable node in current iteration, the proposed method speeds up the decoding significantly. Simulation results show that compared with the standard layered min-sum decoding algorithm, the proposed scheme may reduce about 1/6 iteration numbers for LDPC codes used in DVB-S2, with hardware complexity overhead less than 2%. Key–Words: LDPC code, fast convergence decoding algorithm, layered decoding, min-sum algorithm, hardware implementation 1
A new class of iterative bit flipping (BF) decoding algorithms adapted for low-density parity check (LDPC) convolutional codes is proposed. Compared with Gallager's original BF algorithm, the new BF algorithms improve both the coding gain and the error correction speed. At a bit error rate (BER) of 10 , the best of the new bit-flipping algorithms achieves, after only 6 iterations and with much simpler decoding hardware, a coding gain within 3.5 dB of that of the conventional min-sum belief propagation decoding algorithm.
Non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes when the code length is moderate at the cost of higher decoding complexity. The high complexity is mainly caused by the complicated computations in the check node processing and the large memory requirement. In this paper, a novel check node processing scheme and corresponding VLSI architectures are proposed for the Min-max NB-LDPC decoding algorithm. The proposed scheme first sorts out a limited number of the most reliable variable-to-check (v-to-c) messages, then the check-to-variable (c-to-v) messages to all connected variable nodes are derived independently from the sorted messages without noticeable performance loss. Compared to the previous iterative forward-backward check node processing, the proposed scheme not only significantly reduced the computation complexity, but eliminated the memory required for storing the intermediate messages generated from the forward and backward processes. Inspired by this novel c-to-v message computation method, we propose to store the most reliable v-to-c messages as “compressed” c-to-v messages. The c-to-v messages will be recovered from the compressed format when needed. Accordingly, the memory requirement of the overall decoder can be substantially reduced. Compared to the previous Min-max decoder architecture, the proposed design for a (837, 726) code overGF(25) can achieve the same throughput with only 46% of the area.