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Internet Technology Letters

Design and analysis of stochastic 5G new radio LDPC decoder using adaptive sparse quantization kernel least mean square algorithm for optical satellite communications

R. Krishna Priya, Nitin Nandkumar Sakhare, Ajay Namdeorao Paithane, Ravi Shekhar, M. Sabarimuthu

Published May 19, 2024• 1 citation
Publisher

Abstract

Abstract A Stochastic Low‐Density Parity‐Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal‐to‐noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC‐ASQ‐KLMSA), this paper proposes an area‐efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE‐T standard and used in this study. We examine the ASQ‐KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter‐connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ‐KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub‐node of the degree‐6 VN was changed with an adder‐based 5–1 input grouping sub‐node for the (2048, 1723) code in order to get more accurate results when the check‐to‐variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC‐ASQ‐KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher‐performance stochastic LDPC decoder architecture designed through correlation analysis (HP‐SLDPC‐CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit‐Serial Stochastic Updating(HLDPC‐BSSU), Flexible FPGA‐Based Stochastic Decoder for 5G LDPC codes (FPGA‐SD‐5G‐LDPC), respectively.

DOI
10.1002/itl2.539

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IEEE Access•Jan 1, 2024•28 citations
Abstract A Stochastic Low‐Density Parity‐Check (LDPC) decoder is a type of 5G New Radio standard LDPC decoder that uses stochastic techniques to perform decoding. Stochastic LDPC decoding with 5G NR standard typically uses an iterative process, where messages exchanged among variable nodes (VN), check nodes multiple times. Stochastic LDPC decoders are often used in scenarios where the received signal is subject to varying levels of noise. They will provide improved error correction performance compared to traditional LDPC decoders, especially when dealing with channels with varying signal‐to‐noise ratios in 5G networks. Using the adaptive sparse quantization kernel least mean square algorithm (SLDPC‐ASQ‐KLMSA), this paper proposes an area‐efficient architecture design for a stochastic LDPC decoder. The LDPC code (2048, 1723) is taken from the LOGBASE‐T standard and used in this study. We examine the ASQ‐KLMSA connection effects. Starting with the VN. It makes checking node functioning easier and reduces inter‐connect complexity by capping extrinsic message length at 2 bits. Because of the simplified check node operation in ASQ‐KLMSA, the decoder nodes must exchange messages with a greater degree of accuracy. The 3–3 input grouping sub‐node of the degree‐6 VN was changed with an adder‐based 5–1 input grouping sub‐node for the (2048, 1723) code in order to get more accurate results when the check‐to‐variable messages aren't strong enough. A suggested decoder architecture was determined using a stochastic LDPC decoder developed for TSMC 65 nm process (2048, 1723). Bite error rate, throughput, mean square error, latency, power, and area usage are some of the metrics used to evaluate the effectiveness of the SLDPC‐ASQ‐KLMSA algorithm that has been suggested and implemented in Python. Thus, the proposed approach has attained 34.44%, and 38.39% low mean square error while compared with the existing methods such as higher‐performance stochastic LDPC decoder architecture designed through correlation analysis (HP‐SLDPC‐CA), Higher Throughput and Hardware Efficient Hybrid LDPC Decoder Utilizing Bit‐Serial Stochastic Updating(HLDPC‐BSSU), Flexible FPGA‐Based Stochastic Decoder for 5G LDPC codes (FPGA‐SD‐5G‐LDPC), respectively.
5G technology new radios (5G NR) require high-speed decoders that operate on highly irregular low-density parity-check (LDPC) codes.LDPC decoders have gained significant attention due to their excellent error correction performance.This study evaluates on different algorithms and scheduling techniques used for LDPC decoders.The analysis highlights that Min-Sum-based approaches can reduce the computational complexity compared to the basic sum-product algorithm, while the normalized and extended Min-Sum algorithms provide a better trade-off owing to their accurate value assumptions.Furthermore, different scheduling methods are implied for MS to improve speed and reduce latency.This study provides a comparative analysis of the algorithms and architectures that yield high throughputs without compromising performance efficiency.The LNMS algorithm with a data-level rescheduling technique resolves data dependency issues.This resolves the complexity of CN and VN and improves the throughput, making it suitable for 5G NR applications.The decoded throughput achieved with this scheduling is 7.0 Gbps.This throughput is achieved by maintaining the standard parameters and worst case parameters, such as four/eight iterations, BG1, and a code rate of 0.8/0.5.The evaluated architectures are implemented on Field Programmable Gate Array (FPGA) devices.This study aids in selecting the optimal architecture and scheduling techniques for LDPC decoders by considering various performance standards to deploy wireless networks in 5G and beyond.
In this paper, we present a new microarchitecture of low-density parity-check (LDPC) decoder compliant to the specifications of 5G new-radio (NR) wireless-communication standard. This work suggests a fully-parallel VLSI architecture for this decoder to achieve high throughput. The digital architecture of internal modules as well as system-level design of the LDPC decoder are presented here. The comprehensive bit-error-rate (BER) performance analyses of our LDPC decoder has been performed in additive-white Gaussian-noise (AWGN) channel environment for various number of decoding iterations and bit-quantization. It delivers a BER of 10-6at 1 dB of Eb/N0while decoding for 10 iterations with 7-bits quantization. In addition, FPGA implementation and post-route simulation of the proposed LDPC decoder are carried out that can decode an encoded LDPC code of 26112 code-length for 1/3 code-rate. Our decoder has achieved a throughput of 2.9 Gbps while operating at a clock frequency of 102 MHz. These implementation results are compared with the reported works where our design delivered 20× better throughput compared to the state-of-the-art LDPC decoders.
This paper presents partially-parallel low-density parity-check (LDPC) decoder architecture for binary-input additive-white Gaussian-noise (BIAWGN) channel in 5G new-radio cellular-communication technology based on layered min-sum decoding algorithm. This architecture exploits the iterative decomposition of check-node and variable-node combined-processing unit which leads to area optimization and lower hardware complexity. The proposed VLSI architecture of LDPC decoder processes quasi-cyclic LDPC encoded information which is received as log-likelihood ratios (LLRs) from soft demodulator at the receiver side. It achieves the adequate bit-error-rate (BER) of 10−610 -^{6}10−6 between 2 to 4 dB of bit-energy to noise-power-spectral-density (Eb/N0)(\mathrm{E}_{b}/ \mathrm{N}_{0})(Eb​/N0​) with 10 decoding iterations for various code rates like 1/3, 2/5, 1/2, 2/3, 3/4, 5/6, and 8/9. The VLSI architecture of 5G new-radio LDPC decoder has been field-programmable logic-array (FPGA) prototyped and its implementation results are compared with state-of the-art designs where the proposed LDPC decoder shows lower hardware utilization up to 87%. To the best of our knowledge, this is the first VLSI-architecture of LDPC decoder reported for 5G new-radio compliant to the specifications of enhanced mobile broadband (eMBB).
The paper presents a detailed analysis of the minsum decoding algorithm as applied to low-density parity-check (LDPC) codes used in 5G new radio (NR) systems. With the increasing demand for higher data rates and improved reliability in next-generation wireless communications, LDPC codes have emerged as a pivotal component in 5G NR's coding strategy. The minsum algorithm, known for its simplicity and efficiency in message passing, is evaluated in the context of its performance and practical implementation for these codes. Minsum decoding reduces complexity by approximating the soft-decision values using the minimum of the incoming messages, rather than applying the more computationally expensive operations such as hyperbolic tangent functions. In the context of 5G NR, this approximation makes minsum decoding particularly attractive for hardware implementation, providing a good trade-off between error-correction performance and computational efficiency. The algorithm iteratively updates messages passed along the edges of the Tanner graph, leveraging the sparsity of LDPC codes. This abstract reviews the relevance of minsum decoding to 5G NR LDPC codes, emphasizing its role in balancing performance with low computational requirements, critical in mobile and high-throughput applications.
The expanding demand for high-speed communications has resulted in development of high-throughput error-correcting techniques required by emerging communication standards. Low-Density Parity-Check (LDPC) codes are a class of linear block codes that achieve near-capacity performance and have been selected as part of many digital communication standards. Stochastic computation has been proposed as a hardware efficient approach for decoding LDPC codes. Using stochastic computation, all messages in the iterative decoding process are represented by Bernoulli sequences. Computations on these sequences are performed bit-by-bit using simple logic operations. Furthermore, serial messages used in stochastic decoders help alleviate routing congestion in hardware implementation of decoder. These factors make stochastic decoding a low complexity alternative to implement LDPC decoders. In this dissertation, we analyze the characteristics of stochastic decoding and propose reduced-latency designs for stochastic LDPC decoders to achieve improved performance on various channel models.
This paper presents the novel Stochastic decoding-convolutional neural network (SD-CNN) structure, with the goal of enhancing 5G LDPC code’s decoding efficiency in the presence of correlated noise of the channel. Applying the stochastic approach acts as an alternate technique to fixed-point LDPC decoding to enhance the decoder’s hardware efficiency. In order to improve the efficacy of the decoder, we adopted deep learning method such as Convolutional neural network (CNN). CNNs can be employed for denoising purposes in communication systems, where signals may be compromised by diverse forms of noise while being transmitted, with the aim of enhancing signal quality and dependability. The SD-CNN architecture combines a trained CNN with a stochastic decoder of 5G LDPC codes, thereby utilizing the CNN’s capability to accurately estimate channel noise and, consequently, enhance the error correction capabilities of the decoder. The generated output of the trained CNN is then fed back into the stochastic decoder, creating an iterative process between the SD and CNN that ultimately leads to superior decoding performance. For 5G LDPC code word lengthN=3808N = 3808N=3808, with a base code rateR=1/3R = 1/3R=1/3, the suggested SD-CNN architecture achieves a BER of10−610^{-6}10−6at 0.6 dB of SNR per bit in the strong correlation of channel noise condition, in comparison to SD, which achieves a BER of10−610^{-6}10−6at 3.5 dB of SNR per bit. The results demonstrate that there is a 2.9 dB improvement.