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IEEE International Conference on Electronics, Circuits and Systems (ICECS)

An Enhanced Check-Node Architecture for 5G New Radio LDPC Decoders

Fakhreddine Ghaffari, Khoa Le

Published Nov 28, 2021• 0 citations
Publisher

Abstract

This paper presents an efficient hardware architecture of the Check Node (CN) units for the fifth generation (5G) new-radio Low-Density Parity-Check (LDPC) decoders. The proposed CN architecture is designed by splitting the high-degree CN operations into several phases and simplifying computing circuitry and connection wires. The critical path is shortened while the latency increment for one decoding iteration is negligible. Also, the proposed architecture allows to apply adaptively different offset factors when decoding different CN degree. This technique enhances the error rate and performance of our quantized LDPC decoder. The ASIC synthesis results confirm the advantages of the proposed architecture. This later helps reduce the decoder complexity by up to 30% while the operating frequency is enhanced by 10% compared to the conventional solution.

DOI
10.1109/icecs53924.2021.9665587

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This paper presents an efficient hardware architecture of the Check Node (CN) units for the fifth generation (5G) new-radio Low-Density Parity-Check (LDPC) decoders. The proposed CN architecture is designed by splitting the high-degree CN operations into several phases and simplifying computing circuitry and connection wires. The critical path is shortened while the latency increment for one decoding iteration is negligible. Also, the proposed architecture allows to apply adaptively different offset factors when decoding different CN degree. This technique enhances the error rate and performance of our quantized LDPC decoder. The ASIC synthesis results confirm the advantages of the proposed architecture. This later helps reduce the decoder complexity by up to 30% while the operating frequency is enhanced by 10% compared to the conventional solution.
This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.
This paper presents an Enhanced Offset Min-Sum (EOMS) decoder for Low-Density Parity-Check (LDPC) codes used in the 5th generation (5G) mobile communications. It is observed that a significant part of Variable Nodes (VNs) in the 5G LDPC codes are with degree-1 and are very sensitive to be erroneous, leading to the fact that the decoding performance is generally reduced. In the EOMS decoding, the core check nodes (CN) and extension CNs are processed with different update rules. A new CN -update criterion is also proposed by making use of the third minimum value. As a result, the offset factors are adaptively selected and the error probability of degree-1 VNs is significantly reduced. Simulation results show that the proposed EOMS decoder offers a much better error-correction performance than the state-of-the-art benchmarks for several 5G LDPC codes with a negligible complexity overhead.
The development of the Fifth Generation (5G) New Radio (NR) provides several significant advantages when compared to the fourth generation (4G) Long Term Evolution (LTE) in mobile communications. Due to the outstanding characteristics of Low-Density Parity-Check (LDPC) codes such as high decoding performance, high throughput, low complexity, they have been accepted as the standard codes for the 5G NR. In this paper, we propose two LDPC decoding algorithms: Hybrid Offset Min-Sum (HOMS) and Variable Offset Min-Sum (VOMS), which are aimed at improving the error correction performance. The main idea of the HOMS/VOMS algorithm is to apply modified factors to both variable-nodes and check-nodes updated processing in order to compensate the extrinsic messages overestimation of the MS-based algorithms and increase the protection ability for degree-1 variable-nodes. The simulation results show that at the Bit-Error-Rate (BER) of 10-5, the proposed HOMS/VOMS algorithm achieves the decoding gain up to 0.2 dB compared to the Offset Min-Sum (OMS) algorithm, with a slight increase in decoding complexity.
This paper proposes a unified framework to describe the check node architectures of non-binary low-density parity-check (NB-LDPC) decoders. Forward-backward, syndrome-based, and pre-sorting approaches are first described. Then, they are hybridized in an effective way to reduce the amount of computation required to perform a check node. This paper is specially impacting check nodes of high degrees (or high coding rates). Results of 28-nm ASIC post-synthesis for a check node of degree 12 (i.e., a code rate of 5/6 with a degree of variable equal to 2) are provided for NB-LDPC over GF(64) and GF(256). While simulations show almost no performance loss, the new proposed hybrid implementation check node increases the hardware and the power efficiency by a factor of six compared with the classical forward-backward architecture. This leads to the first ever reported implementation of a degree 12 check node over GF(256), and these preliminary results open the road to high decoding throughput, high rate, and high-order Galois field NB-LDPC decoder with a reasonable hardware complexity.
One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit.Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages.This block significantly affects the decoding performance, as well as the hardware implementation complexity.In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages.Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm.The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes.The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance.More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our innovative approach presents a fully parallel architecture that is precisely engineered to cater to the demanding high-throughput requirements of enhanced Mobile Broadband (eMBB) applications. To ensure smooth computation in the MS algorithm, we use the Sub-Optimal Low-Latency (SOLL) technique to optimize the critical check node process. Thus, our design has the potential to greatly benefit certain Ultra-Reliable Low-Latency Communications (URLLC) scenarios. We conducted precise Bit Error Rate (BER) performance analysis on our LDPC decoder using a Hardware Description Language (HDL) Co-Simulation (MATLAB/Simulink/ModelSim) for two codeword rates (2/3 and 1/3), simulating the challenging Additive White Gaussian Noise (AWGN) channel environment.