Quantum error correction (QEC) is the central building block of fault-tolerant quantum computation but the design of QEC codes may not always match the underlying hardware. To tackle the discrepancy between the quantum hardware and QEC codes, we propose a synthesis framework that can implement and optimize the surface code onto superconducting quantum architectures. In particular, we divide the surface code synthesis into three key subroutines. The first two optimize the mapping of data qubits and ancillary qubits including syndrome qubits on the connectivity-constrained superconducting architecture, while the last subroutine optimizes the surface code execution by rescheduling syndrome measurements. Our experiments on mainstream superconducting architectures demonstrate the effectiveness of the proposed synthesis framework. Especially, the surface codes synthesized by the proposed automatic synthesis framework can achieve comparable or even better error correction capability than manually designed QEC codes.
Quantum error correction (QEC) is the central building block of fault-tolerant quantum computation but the design of QEC codes may not always match the underlying hardware. To tackle the discrepancy between the quantum hardware and QEC codes, we propose a synthesis framework that can implement and optimize the surface code onto superconducting quantum architectures. In particular, we divide the surface code synthesis into three key subroutines. The first two optimize the mapping of data qubits and ancillary qubits including syndrome qubits on the connectivity-constrained superconducting architecture, while the last subroutine optimizes the surface code execution by rescheduling syndrome measurements. Our experiments on mainstream superconducting architectures demonstrate the effectiveness of the proposed synthesis framework. Especially, the surface codes synthesized by the proposed automatic synthesis framework can achieve comparable or even better error correction capability than manually designed QEC codes.
In this paper, we formally describe the three challenges of mapping surface code on superconducting devices, and present a comprehensive synthesis framework to overcome these challenges. The proposed framework consists of three optimizations. First, we adopt a geometrical method to allocate data qubits which ensures the existence of shallow syndrome extraction circuit. The proposed data qubit layout optimization reduces the overhead of syndrome extraction and serves as a good initial point for following optimizations. Second, we only use bridge qubits enclosed by data qubits and reduce the number of bridge qubits by merging short path between data qubits. The proposed bridge qubit optimization reduces the probability of bridge qubit conflicts and further minimizes the syndrome extraction overhead. Third, we propose an efficient heuristic to schedule syndrome extractions. Based on the proposed data qubit allocation, we devise a good initial schedule of syndrome extractions and further refine this schedule to minimize the total time needed by a complete surface code error detection cycle. Our experiments on mainsstream superconducting quantum architectures have demonstrated the efficiency of the proposed framework.
Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of 35ns with a fidelity of F=99.96%. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50\% to ≈1.2% and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.
Quantum error correction is a critical technique for transitioning from noisy intermediate-scale quantum devices to fully fledged quantum computers. The surface code, which has a high threshold error rate, is the leading quantum error correction code for two-dimensional grid architecture. So far, the repeated error correction capability of the surface code has not been realized experimentally. Here, we experimentally implement an error-correcting surface code, the distance-three surface code which consists of 17 qubits, on the Zuchongzhi 2.1 superconducting quantum processor. By executing several consecutive error correction cycles, the logical error can be significantly reduced after applying corrections, achieving the repeated error correction of surface code for the first time. This experiment represents a fully functional instance of an error-correcting surface code, providing a key step on the path towards scalable fault-tolerant quantum computing.
The pursuit of scalable quantum computing is intrinsically limited by qubit decoherence, making robust quantum error correction (QEC) techniques crucial. As a leading solution, the topological surface code offers inherent protection against local noise. This study presents the first comprehensive implementation and quantitative characterization of a full surface code pipeline, which includes encompassing lattice construction, multi-round syndrome extraction, and MWPM decoding, using the high-level Qrisp programming framework. The entire pipeline was executed on IQM superconducting quantum processors to provide an empirical assessment under current noisy intermediate-scale quantum (NISQ) conditions. Our experimental data definitively show that the system operates significantly below the fault-tolerance threshold. Crucially, a quantitative resource analysis isolates and establishes the lack of native qubit reset on the hardware as the dominant architectural bottleneck. This constraint forces the physical qubit count to scale as d2+(d2−1)T, effectively preventing scaling to larger code distances (d) and execution times (T) on current devices. The work confirms Qrisp’s capability to support advanced QEC protocols, demonstrating that high-level abstraction can reduce implementation complexity by simplifying scheduling and mapping, thereby facilitating deeper experimental analysis of hardware limitations.
Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.
Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding.
This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.