Quantum error correction is a critical technique for transitioning from noisy intermediate-scale quantum devices to fully fledged quantum computers. The surface code, which has a high threshold error rate, is the leading quantum error correction code for two-dimensional grid architecture. So far, the repeated error correction capability of the surface code has not been realized experimentally. Here, we experimentally implement an error-correcting surface code, the distance-three surface code which consists of 17 qubits, on the Zuchongzhi 2.1 superconducting quantum processor. By executing several consecutive error correction cycles, the logical error can be significantly reduced after applying corrections, achieving the repeated error correction of surface code for the first time. This experiment represents a fully functional instance of an error-correcting surface code, providing a key step on the path towards scalable fault-tolerant quantum computing.
Quantum error correction is a critical technique for transitioning from noisy intermediate-scale quantum devices to fully fledged quantum computers. The surface code, which has a high threshold error rate, is the leading quantum error correction code for two-dimensional grid architecture. So far, the repeated error correction capability of the surface code has not been realized experimentally. Here, we experimentally implement an error-correcting surface code, the distance-three surface code which consists of 17 qubits, on the Zuchongzhi 2.1 superconducting quantum processor. By executing several consecutive error correction cycles, the logical error can be significantly reduced after applying corrections, achieving the repeated error correction of surface code for the first time. This experiment represents a fully functional instance of an error-correcting surface code, providing a key step on the path towards scalable fault-tolerant quantum computing.
Quantum error correction [1, 2, 3, 4] provides a path to reach practical quantum computing by combining multiple physical qubits into a logical qubit, where the logical error rate is suppressed exponentially as more qubits are added. However, this exponential suppression only occurs if the physical error rate is below a critical threshold. Here, we present two below-threshold surface code memories on our newest generation of superconducting processors, Willow: a distance-7 code, and a distance-5 code integrated with a real-time decoder. The logical error rate of our larger quantum memory is suppressed by a factor of Λ=2.14±0.02 when increasing the code distance by two, culminating in a 101-qubit distance-7 code with 0.143% ± 0.003% error per cycle of error correction. This logical memory is also beyond break-even, exceeding its best physical qubit’s lifetime by a factor of 2.4±0.3 . Our system maintains below-threshold performance when decoding in real time, achieving an average decoder latency of 63 μs at distance-5 up to a million cycles, with a cycle time of 1.1 μs. We also run repetition codes up to distance-29 and find that logical performance is limited by rare correlated error events occurring approximately once every hour, or 3×109 cycles. Our results present device performance that, if scaled, could realize the operational requirements of large scale fault-tolerant quantum algorithms.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).
Fault-tolerant logical operations are fundamental for scalable quantum computation. Here, we report the experimental realization of lattice-surgery operations between a pair of distance-three surface-code logical qubits on a planar superconducting processor. During repeated syndrome extraction cycles, the logical qubits exhibit per-cycle error rates of 0.0365(2) and 0.0282(1), respectively, after leakage events are rejected. By leveraging joint initialization and lattice splitting, we deterministically prepare a logical Bell state, confirming genuine bipartite entanglement via the error-corrected logical state fidelity. We further execute a two-qubit Deutsch-Jozsa algorithm at the logical level to demonstrate algorithmic utility in a fault-tolerant framework. Finally, to achieve universal control, we implement magic-state injection and gate teleportation to realize continuous non-Clifford rotations about the logical X axis. For the logical RX(π/4) gate, we achieve a logical gate fidelity of 0.943−9+10 conditioned on the absence of detected errors. These results establish lattice surgery as a practical and versatile paradigm for logical computation in near-term surface-code architectures, representing a critical milestone toward scalable fault-tolerant quantum advantage in superconducting circuits.
By using a superconducting processor, Google Quantum AI group demonstrated that a logic qubit realized by surface code of quantum error correction performs better when the number of physical qubits increases. Two surface codes to encode logic qubits for scaling are realized experimentally, with multiple cycles of quantum error correcting assisted by ancillary qubits. This result can be considered as an important step toward fault-tolerant quantum computers. In this review paper, we introduce briefly the mechanism of quantum error correction. As an example, Shor’s nine-qubit error correction code is explained. Then, the new experiments of Google quantum AI group are introduced to show their significance in scaling. The advances in other quantum error correction experiments are also reviewed. Finally, the development of quantum computers is discussed.
A remarkable characteristic of quantum computing is the potential for reliable computation despite faulty qubits. This can be achieved through quantum error correction, which is typically implemented by repeatedly applying static syndrome checks, permitting correction of logical information. Recently, the development of time-dynamic approaches to error correction has enabled different codes and implementations that do not rely on static syndrome measurements. Here we experimentally demonstrate three time-dynamic implementations of the surface code, each offering a distinct solution to hardware design challenges faced by surface code realizations. First, we embed the surface code on a hexagonal lattice, reducing the necessary couplings per qubit from four to three. Second, we walk a surface code, swapping the role of data and measure qubits each round, achieving error correction with built-in removal of accumulated non-computational errors. Finally, we realize the surface code using iSWAP gates instead of the traditional CNOT, extending the set of viable gates for error correction without additional overhead. We measure the error suppression factor when scaling from distance-3 to distance-5 codes of Λ35,hex = 2.15(2), Λ35,walk = 1.69(6) and Λ35,iSWAP = 1.56(2), achieving state-of-the-art error suppression for each. Our work demonstrates that dynamic circuit approaches meet the demands for fault tolerance and enable alternative strategies for scalable hardware design. Typical quantum error correcting codes assign fixed roles to the underlying physical qubits. Now the performance benefits of alternative, dynamic error correction schemes have been demonstrated on a superconducting quantum processor.
Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.