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arXiv:2607.01473

Surface code logical operations on a superconducting quantum processor

Weiping Lin, Shaojun Guo, Yuwei Ma, Zhengzhong Yi, Kai Zhang, Jiahao Bei, Jianbin Cai, Sirui Cao, Danning Chen, Guoben Chen, Jianguo Chen, Kefu Chen, Xiawei Chen, Zhe Chen, Zhiyuan Chen, Zihua Chen, Wenhao Chu, Hui Deng, Xun Ding, Zhuzhengqi Ding, Yajie Du, Bo Fan, Daojin Fan, Yuanhao Fu, Dongxin Gao, Ming Gong, Jiacheng Gui, Cheng Guo, Lianchen Han, Tan He, Linyin Hong, Yisen Hu, He-Liang Huang, Yong-Heng Huo, Chenyan Jiang, Lei Jiang, Tao Jiang, Wei Jiang, Zuokai Jiang, Dayu Li, Dongdong Li, Jiaqi Li, Jinjin Li, Junyun Li, Shaowei Li, Wei Li, Xu Li, Yuan Li, Yuhuai Li, Futian Liang, Nanxing Liao, Jin Lin, Maliang Liu, Yancheng Liu, Haoxin Lou, Kailiang Nan, Meijuan Nie, Le Niu, Wenyi Peng, Haoran Qian, Hao Rong, Tao Rong, Yanyan Shao, Huiyan Shen, Qiong Shen, Ganlin Song, Hong Su, Feifan Su, Chenyin Sun, De Sun, Liangchao Sun, Tianzuo Sun, Yingxiu Sun, Yimeng Tan, Jun Tan, Shibiao Tang, Yueyang Tang, Wenbing Tu, Jiafei Wang, Biao Wang, Chang Wang, Chen Wang, Chu Wang, Jian Wang, Rui Wang, Shengtao Wang, Xinzhe Wang, Zhi Wang, Zuolin Wei, Gang Wu, Yulin Wu, Hongjun Xia, Shouzhong Xia, Shiyong Xie, Zhilin Xie, Liang Xiong, Jianping Xu, Yan Xu, Yu Xu, Chun Xue, Kai Yan, Xin Yan, Weifeng Yang, Xinpeng Yang, Yang Yang, Yicheng Yang, Yangsen Ye, Zhenping Ye, Jianghan Yin, Chong Ying, Jiale Yu, Qinjing Yu, Chen Zha, Shaoyu Zhan, Cha Zhang, Fang Zhang, Haibin Zhang, He Zhang, Huanmei Zhang, Kaili Zhang, Qipeng Zhang, Shijia Zhang, Wen Zhang, Xin Zhang, Yiming Zhang, Yongzhuo Zhang, Ziying Zhang, Guming Zhao, Xintao Zhao, Youwei Zhao, Zhong Zhao, Luyuan Zheng, Fei Zhou, Liang Zhou, Naibin Zhou, Chengjun Zhu, Qingling Zhu, Yongsheng Zhu, Guihong Zou, Haonan Zou, Qiang Zhang, Chao-Yang Lu, Jianxin Chen, Cheng-Zhi Peng, Fusheng Chen, XiaoBo Zhu, Jian-Wei Pan

quant-phSubmitted Jul 1, 2026• Announced Jul 3, 2026• 0 citations
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Abstract

Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.

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Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded ZZ logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.

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Abstract Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded Z Z logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.

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Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.

quant-pharXiv:2610.23840•Oct 19, 2026•0 citations
Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.
Fault-tolerant logical operations are fundamental for scalable quantum computation. Here, we report the experimental realization of lattice-surgery operations between a pair of distance-three surface-code logical qubits on a planar superconducting processor. During repeated syndrome extraction cycles, the logical qubits exhibit per-cycle error rates of 0.0365(2)0.0365(2)0.0365(2) and 0.0282(1)0.0282(1)0.0282(1), respectively, after leakage events are rejected. By leveraging joint initialization and lattice splitting, we deterministically prepare a logical Bell state, confirming genuine bipartite entanglement via the error-corrected logical state fidelity. We further execute a two-qubit Deutsch-Jozsa algorithm at the logical level to demonstrate algorithmic utility in a fault-tolerant framework. Finally, to achieve universal control, we implement magic-state injection and gate teleportation to realize continuous non-Clifford rotations about the logical XXX axis. For the logical RX(π/4)R_{X}(π/4)RX​(π/4) gate, we achieve a logical gate fidelity of 0.943−9+100.943_{-9}^{+10}0.943−9+10​ conditioned on the absence of detected errors. These results establish lattice surgery as a practical and versatile paradigm for logical computation in near-term surface-code architectures, representing a critical milestone toward scalable fault-tolerant quantum advantage in superconducting circuits.
Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded ZZ logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
We present a fault-tolerant quantum-memory architecture that concatenates four distance-t rotated surface-code patches with the [[4,2,2]] outer code, encoding two logical qubits at code distance d = 2t in a physical footprint of N < 2(2t+1)^2 qubits on a square lattice with nearest-neighbor connectivity. The outer-code stabilizer generators XXXX and ZZZZ, each of physical weight 4t, are measured in situ via verified Greenberger-Horne-Zeilinger (GHZ) ancillae distributed through narrow corridors between adjacent patches, without lattice surgery or long-range gates. The outer-code gadgets introduce hyperedge fault mechanisms, but by design each decomposes into graphlike components, so the complete syndrome is decoded by a single minimum-weight-perfect-matching pass. Circuit-level simulations show logical error rates that scale as p^t, consistent with distance-2t protection. Finally, we implement the construction experimentally on a 105-qubit Willow superconducting processor in both the ZZ and XX memory bases. With the correlated-matching decoder, increasing the code distance from d = 4 to d = 6 reduces the block logical error rate by a factor of 1.52. The construction thus provides a near-term testbed for concatenated architectures beyond the standard surface code.
Abstract Quantum error correction is needed for quantum computers to be capable of executing algorithms using hundreds of logical qubits in a fault-tolerant manner. Recent experiments have progressed towards this by demonstrating sufficiently low error rates for state preservation of a single logical qubit. However, quantum computation algorithms also require that these logical qubits can be entangled and that gate operations can be performed on them. Lattice surgery is a technique that offers a practical approach for implementing such gates, particularly in planar quantum processor layouts. Here we demonstrate lattice surgery between two distance-three repetition-code qubits by splitting a single distance-three surface-code qubit. Using a quantum circuit that is fault-tolerant for bit-flip errors, we achieve an improvement in the value of the decoded Z Z logical two-qubit observable compared with a similar non-encoded circuit. We therefore demonstrate the functional building blocks needed for lattice-surgery operations on larger-distance codes based on superconducting circuits.
Neural decoders for quantum error correction have achieved high accuracy on surface code memory experiments, but practical fault-tolerant computation requires decoders that transfer across devices, noise conditions, and logical operations. We introduce a modular graph-recurrent decoder designed for this setting. Built from reusable local syndrome encoders, it is pretrained in simulation and fine-tuned to hardware using a common pipeline, with only lightweight spatial aggregation adapted between experiments. The decoder performs competitively on conventional memory benchmarks, outperforming minimum-weight perfect matching (MWPM) at distances 3 and 5 on an IBM Nighthawk-generation processor and closely approaching AlphaQubit on Google's below-threshold hardware data. We then test the framework in two settings beyond memory decoding on the same IBM device. First, in an XXX-type stability experiment, we continuously tune the effective measurement error rate using a variable pre-readout rotation and train a single decoder jointly across the resulting noise range. It matches or outperforms MWPM across the sweep without requiring a separately calibrated decoder for each setting. Second, we decode a ZZZZZZ-merge lattice-surgery experiment between two distance-3 surface-code patches, improving the decoded correlation between the merge outcome and the final ZZZZZZ parity relative to MWPM on real hardware. Together, these experiments demonstrate neural decoding that is portable not only across hardware, but also across qualitatively different surface code observables and logical operations, using models trainable on single-GPU academic resources.
Quantum error correction can suppress logical errors exponentially with code distance when physical noise is below threshold. Realizing this on hardware requires tight coordination among quantum gates, mid-circuit measurements, and qubit coherence. Device variation, noise asymmetry, and correlations across space and time complicate the translation of these capabilities into logical error suppression. Here, we study rotated surface-code memory on an IBM Nighthawk r2 processor. Performance varies across tested processor placements, which we attribute to differences in qubit quality. We optimize the code by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the optimized syndrome extraction circuit reduces the median per-round logical error rate by factors of 3.8 in the X basis and 1.4 in the Z basis. In memory experiments of up to 150 rounds, the distance advantage weakens, alongside long-lived correlations that may reflect a persistent error component. Under our optimization recipe, increasing the protected distance from 3 to 6 while holding the other distance fixed reduces the per-round logical error rate from 0.53% to 0.24% in Z memory and from 0.52% to 0.22% in X memory. The corresponding error-suppression factors under maximum-likelihood decoding are 1.68 and 1.85. These results connect circuit compilation and optimization to surface-code memory performance and limitations, and motivate QPU and QEC circuit codesign for fault-tolerant quantum computing primitives on current cloud hardware.