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arXiv:2506.09028

Optimizing Superconducting Three-Qubit Gates for Surface-Code Error Correction

Stephan Tasler, Josias Old, Lukas Heunisch, Verena Feulner, Timo Eckstein, Markus Müller, Michael J. Hartmann

Published Jan 1, 2025• 0 citations
arXivHTMLPDF

Abstract

Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of $35\,$ns with a fidelity of F$=99.96 \, \%$. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50\% to $\approx 1.2\,\%$ and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.

DOI
10.34734/fzj-2025-05066

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Quantum error correction (QEC) is one of the crucial building blocks for developing quantum computers that have significant potential for reaching a quantum advantage in applications. Prominent candidates for QEC are stabilizer codes for which periodic readout of stabilizer operators is typically implemented via successive two-qubit entangling gates, and is repeated many times during a computation. To improve QEC performance, it is thus beneficial to make the stabilizer readout faster and less prone to fault-tolerance-breaking errors. Here we design a 3-qubit CZZ gate for superconducting transmon qubits that maps the parity of two data qubits onto one measurement qubit in a single step. We find that the gate can be executed in a duration of 35 35\,35ns with a fidelity of F=99.96 %=99.96 \, \%=99.96%. To optimize the gate, we use an error model obtained from the microscopic gate simulation to systematically suppress Pauli errors that are particularly harmful to the QEC protocol. Using this error model, we investigate the implementation of this 3-qubit gate in a surface code syndrome readout schedule. We find that for the rotated surface code, the implementation of CZZ gates increases the error threshold by nearly 50% to ≈1.2 %\approx 1.2\,\%≈1.2% and decreases the logical error rate, in the experimental relevant regime, by up to one order of magnitude, compared to the standard CZ readout protocol. We also show that for the unrotated surface code, strictly fault-tolerant readout schedules can be found. This opens a new perspective for below-threshold surface-code error correction, where it can be advantageous to use multi-qubit gates instead of two-qubit gates to obtain a better QEC performance.
Stabilizer quantum error correction (QEC) codes, in particular topological surface codes, are prime candidates to enable practical quantum computing. While it is widely believed that strictly fault-tolerant protocols can only be implemented using single- and two-qubit gates, several quantum computing platforms, including trapped ions, neutral atoms, and superconducting qubits, support native multi-qubit operations. In this Letter, we show that stabilizer measurement circuits for unrotated surface codes can be fault tolerant using single auxiliary qubits and three-qubit gates. These gates enable lower-depth circuits with fewer fault locations and potentially shorter QEC cycle times. We find that in an optimistic parameter regime where fidelities of three-qubit gates are the same as those of two-qubit gates, the logical error rate can be up to one order of magnitude lower and the threshold significantly higher, increasing from ≈0.63% to ≈0.83%. Our results, applicable to a wide range of platforms, motivate further investigation into multi-qubit gates for fault-tolerant QEC as they can offer substantial time and physical qubit resource advantages to reach a given target logical error rate.
Quantum error correction (QEC) requires the execution of deep quantum circuits with large numbers of physical qubits to protect information against errors. Designing protocols that can reduce gate and space-time overheads of QEC is therefore crucial to enable more efficient QEC in near-term experiments. Multiqubit gates offer a natural path toward fast and low-depth stabilizer measurement circuits. However, they typically introduce high-weight correlated errors that can degrade the circuit-level distance, leading to slower scalings of the logical error probabilities. In this Letter, we show how to realize fast and efficient surface code stabilizer readout using only two singly controlled z gates acting simultaneously on two target qubits, i.e., two CZ_{2} gates-instead of four cz. We show that this scheme is fault tolerant and provide a blueprint for implementation in Rydberg atom arrays. We derive the time-optimal pulses implementing the gates and perform extensive QEC numerical simulations with Rydberg decay errors. Compared to the standard protocol using four cz gates, our scheme is faster, uses fewer gates, and crucially maintains fault tolerance with comparable logical error probabilities. Fault-tolerant generalizations of this scheme to biased and erasure-dominant noise models, as well as to other QEC codes such as quantum Low-Density Parity-Check codes, are also discussed.
Multiqubit gates that involve three or more qubits are usually thought to be of little significance for fault-tolerant quantum error correction because single gate faults can lead to errors of high Pauli weight. However, recent works have shown that multiqubit gates can be beneficial for measurement-free fault-tolerant quantum error correction and for fault-tolerant stabilizer readout in unrotated surface codes. In this work, we investigate multiqubit Rydberg gates that are useful for fault-tolerant quantum error correction in single-species neutral-atom platforms and can be implemented with global laser pulses that do not individually address atomic sites. We develop an open-source Python package to generate analytical, few-parameter pulses that implement the desired gates while minimizing gate errors due to Rydberg-state decay. The tool also allows us to identify parameter-optimal pulses, characterized by a minimal parameter count for the pulse ansatz. Measurement-free quantum error correction protocols require CCZ gates, which we analyze for atoms arranged in symmetric and asymmetric configurations. We investigate the performance of these schemes for various single-, two-, and three-qubit gate error rates, showing that break-even performance of measurement-free QEC is within reach of current hardware. Moreover, we study Floquet quantum error correction protocols that comprise two-body stabilizer measurements. Those can be realized using global three-qubit gates, and we show that this can lead to a significant reduction in shuttling operations. Simulations with realistic circuit-level noise indicate that applying three-qubit gates for stabilizer measurements in Floquet codes can yield competitive logical qubit performance in experimentally relevant error regimes.
Error correcting codes use multi-qubit measurements to realize fault-tolerant quantum logic steps. In fact, the resources needed to scale-up fault-tolerant quantum computing hardware are largely set by this task. Tailoring next-generation processors for joint measurements, therefore, could result in improvements to speed, accuracy, or cost -- accelerating the development large-scale quantum computers. Here, we motivate such explorations by analyzing an unconventional surface code based on multi-body interactions between superconducting transmon qubits. Our central consideration, Hardware Optimized Parity (HOP) gates, achieves stabilizer-type measurements through simultaneous multi-qubit conditional phase accumulation. Despite the multi-body effects that underpin this approach, our estimates of logical faults suggest that this design can be at least as robust to realistic noise as conventional designs. We show a higher threshold of 1.25×10−31.25 \times 10^{-3}1.25×10−3 compared to the standard code's 0.79×10−30.79 \times 10^{-3}0.79×10−3. However, in the HOP code the logical error rate decreases more slowly with decreasing physical error rate. Our results point to a fruitful path forward towards extending gate-model platforms for error correction at the dawn of its empirical development.
Quantum computation holds the promise of solving certain complex problems exponentially faster than classical computers. However, the high prevalent noise in current quantum devices impedes the accurate execution of even basic algorithms. This can be remedied by protecting quantum information with a quantum error-correcting code, where the logical information of an algorithmic qubit is spread across multiple physical qubits. Individual quantum errors are then located and corrected by the fault-tolerant measurement of multi-qubit stabilizer operators (parity checks). Unfortunately, error correction and fault tolerance both impose large demands on the qubit overhead: hundreds to thousands of physical qubits per logical qubit. We reduce the spacetime cost of fault tolerance by redesigning key building blocks of an error-corrected quantum computer. First, we develop a combinatorial proof with flag fault tolerance that exponentially reduces the extra qubits needed to measure a stabilizer of any size, while tolerating one fault. We leverage these proofs to then design state preparation circuits for the Steane and Golay codes with 100% yield. Next, we improve error correction on a planar layout by showing that a distance-four code encoding six logical qubits protects information as well as the distance-five surface code, using one-tenth as many physical qubits. Finally, we optimize the time overhead of logical gates in surface code quantum computers by protecting measurement results with a classical code, cutting computation time by a factor of two to six. Our hardware-agnostic optimizations of fault tolerance overheads thus suggest new routes to advance the timeline of error-free quantum computing.
Current quantum processors are fragile, noisy and fairly limited in both quantity and quality with tens of qubits and physical error rates of around 10^-3. To realize practical quantum applications, however, error rates need to be below 10^-15 across millions of qubits. To bridge this gap and fully harness the potential of quantum computers, quantum error correction (QEC) is essential. QEC codes are designed to protect quantum information by redundantly encoding it onto multiple physical qubits. This encoding allows for the detection and correction of local errors affecting individual qubits, e.g., through stabilizer measurements. Importantly, if the physical error rates are below a specific threshold, QEC codes can exponentially suppress logical error rates by increasing the number of physical qubits involved. This is essential for achieving fault-tolerant computations, which are key to unlocking the full potential of quantum computers. The work presented in this thesis focuses on the implementation and optimization of small-scale QEC experiments using the surface code and flux-tunable superconducting qubits (Transmons). It addresses several key challenges: enhancing two-qubit gate fidelity in Surface-4 (Chapter 2), implementing an error-detection code with Surface-7 (Chapter 3), automating the calibration and benchmarking of the building blocks in Surface-17 (Chapter 4), reducing leakage into higher excited states with leakage reduction units (Chapter 5), assessing and enhancing the performance of logical qubits (Chapters 7 and 8).