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arXiv:2111.13729

Mapping Surface Code to Superconducting Quantum Processors

Anbang Wu, Gushu Li, Hezi Zhang, Gian Giacomo Guerreschi, Yufei Ding, Yuan Xie

Published Nov 26, 2021• 0 citations
arXivHTMLPDF

Abstract

In this paper, we formally describe the three challenges of mapping surface code on superconducting devices, and present a comprehensive synthesis framework to overcome these challenges. The proposed framework consists of three optimizations. First, we adopt a geometrical method to allocate data qubits which ensures the existence of shallow syndrome extraction circuit. The proposed data qubit layout optimization reduces the overhead of syndrome extraction and serves as a good initial point for following optimizations. Second, we only use bridge qubits enclosed by data qubits and reduce the number of bridge qubits by merging short path between data qubits. The proposed bridge qubit optimization reduces the probability of bridge qubit conflicts and further minimizes the syndrome extraction overhead. Third, we propose an efficient heuristic to schedule syndrome extractions. Based on the proposed data qubit allocation, we devise a good initial schedule of syndrome extractions and further refine this schedule to minimize the total time needed by a complete surface code error detection cycle. Our experiments on mainsstream superconducting quantum architectures have demonstrated the efficiency of the proposed framework.

DOI
10.48550/arxiv.2111.13729

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In this paper, we formally describe the three challenges of mapping surface code on superconducting devices, and present a comprehensive synthesis framework to overcome these challenges. The proposed framework consists of three optimizations. First, we adopt a geometrical method to allocate data qubits which ensures the existence of shallow syndrome extraction circuit. The proposed data qubit layout optimization reduces the overhead of syndrome extraction and serves as a good initial point for following optimizations. Second, we only use bridge qubits enclosed by data qubits and reduce the number of bridge qubits by merging short path between data qubits. The proposed bridge qubit optimization reduces the probability of bridge qubit conflicts and further minimizes the syndrome extraction overhead. Third, we propose an efficient heuristic to schedule syndrome extractions. Based on the proposed data qubit allocation, we devise a good initial schedule of syndrome extractions and further refine this schedule to minimize the total time needed by a complete surface code error detection cycle. Our experiments on mainsstream superconducting quantum architectures have demonstrated the efficiency of the proposed framework.
Quantum error correction (QEC) is the central building block of fault-tolerant quantum computation but the design of QEC codes may not always match the underlying hardware. To tackle the discrepancy between the quantum hardware and QEC codes, we propose a synthesis framework that can implement and optimize the surface code onto superconducting quantum architectures. In particular, we divide the surface code synthesis into three key subroutines. The first two optimize the mapping of data qubits and ancillary qubits including syndrome qubits on the connectivity-constrained superconducting architecture, while the last subroutine optimizes the surface code execution by rescheduling syndrome measurements. Our experiments on mainstream superconducting architectures demonstrate the effectiveness of the proposed synthesis framework. Especially, the surface codes synthesized by the proposed automatic synthesis framework can achieve comparable or even better error correction capability than manually designed QEC codes.
The pursuit of scalable quantum computing is intrinsically limited by qubit decoherence, making robust quantum error correction (QEC) techniques crucial. As a leading solution, the topological surface code offers inherent protection against local noise. This study presents the first comprehensive implementation and quantitative characterization of a full surface code pipeline, which includes encompassing lattice construction, multi-round syndrome extraction, and MWPM decoding, using the high-level Qrisp programming framework. The entire pipeline was executed on IQM superconducting quantum processors to provide an empirical assessment under current noisy intermediate-scale quantum (NISQ) conditions. Our experimental data definitively show that the system operates significantly below the fault-tolerance threshold. Crucially, a quantitative resource analysis isolates and establishes the lack of native qubit reset on the hardware as the dominant architectural bottleneck. This constraint forces the physical qubit count to scale as d2+(d2−1)T, effectively preventing scaling to larger code distances (d) and execution times (T) on current devices. The work confirms Qrisp’s capability to support advanced QEC protocols, demonstrating that high-level abstraction can reduce implementation complexity by simplifying scheduling and mapping, thereby facilitating deeper experimental analysis of hardware limitations.
Modular quantum computing is a leading candidate for scalable fault tolerant quantum computation. Performing lattice surgery using surface code patches in different modules requires the use of inter-module gates that are noisier than the local gates. Furthermore, the merged layouts during lattice surgery expose multiple directions in which hook errors can propagate to reduce the fault distance. Existing hook-avoiding schedules either increase the syndrome extraction circuit depth, or let link faults propagate into the bulk. We introduce a seam construction that allows splitting arbitrary merged rotated surface code layout into smaller patches with uniform boundaries that could keep their own hook-avoiding N/Z shaped schedule. At the seam we split weight-4 stabilizers into pairs of weight-2 stabilizers that are mediated through a Bell pair and measured within a CNOT depth of 4. We also employ the use of three-qubit CXX\texttt{CXX}CXX gates for parity measurements at the seam to maintain the minimum CNOT depth. Through this seam construction, we confine the elevated link error at the seam, protecting the bulk from higher error rate. We also give a custom detector annotator for such seams that can find the detector space, annotate detectors in the Stim circuits, and ensure that they are suitable to use by matching decoders. We implement our construction for the logical Pauli-XXXXXX measurement lattice surgery and a cross-shaped spatial junction and sweep the link error rate from 101010 times to 100100100 times a fixed bulk error rate, and show that our construction gives the lowest and most stable logical error rate than the other frameworks compared here.
Quantum error-correcting codes are a vital technology for demonstrating reliable quantum computation. They require data qubits for encoding quantum information and ancillary qubits for taking error syndromes necessary for error correction. The need for a large number of ancillary qubits is an overhead specific to quantum computing, and it prevents the scaling of quantum computers to a useful size. In this work, we propose a framework for generating efficient syndrome measurement circuits with a few ancillary qubits in CSS codes and provide a method to minimize the total number of physical qubits in general settings. We demonstrated our proposal by applying it to surface codes, and we generated syndrome measurement circuits under several constraints of total qubit count. As a result, we find that balanced data and ancillary qubit counts achieve the lower logical error rates under a fixed total number of physical qubits. This result indicates that using fewer ancillary qubits than the number of stabilizers can be effective for reducing logical error rates in a practical noise model.
Fault-tolerant quantum computation requires logical operations that manipulate encoded information while preserving quantum error-correction protection. In planar surface-code architectures, code deformation and lattice surgery provide a local, measurement-based route to such operations. Here we experimentally realize key elements of patch-based surface-code logical processing on a 107-qubit superconducting quantum processor. We first implement a reusable primitive layer comprising merge and split, patch expansion and shrinkage, and deformations mediated by domain walls and twist defects. We then compose these primitives to realize logical state routing, the logical controlled-NOT gate, and the single-qubit Hadamard and phase gates, which together form a Clifford-generating set. All operations are implemented on distance-three rotated surface-code patches with multi-round syndrome extraction and neural-network decoding, without post-selection. Our results advance superconducting surface-code experiments from protected logical memory to active, patch-based fault-tolerant logical operations.
The surface code is a prominent topological error-correcting code exhibiting high fault-tolerance accuracy thresholds. Conventional schemes for error correction with the surface code place qubits on a planar grid and assume native CNOT gates between the data qubits with nearest-neighbor ancilla qubits.Here, we present surface code error-correction schemes using only Pauli measurements on single qubits and on pairs of nearest-neighbor qubits. In particular, we provide several qubit layouts that offer favorable trade-offs between qubit overhead, circuit depth and connectivity degree. We also develop minimized measurement sequences for syndrome extraction, enabling reduced logical error rates and improved fault-tolerance thresholds.Our work applies to topologically protected qubits realized with Majorana zero modes and to similar systems in which multi-qubit Pauli measurements rather than CNOT gates are the native operations.