To realize the potential of quantum computing, a compact integrated system with millions of qubits and control electronics is required. Existing analog schemes are challenging for the compact system with a high I/O density and wiring requirement. In this paper, a new digital assembly scheme providing high-density I/O (>10000 per mm2) is proposed. Qubits can be heterogeneously integrated with digital superconducting control electronics on a System-on-Wafer Superconducting Silicon Interconnect Fabric which is experimentally validated in this work. The key potential advantages include nanoseconds of control/readout cycle, 10–4qubit error rate, 0.2 mW system power dissipation per qubit. The dies can be assembled on the SoW platform with ≤ 100 µm inter-dielet spacing through the Au interlayer technology, which is demonstrated to be fine pitch (≤10 um), quantum-compatible (30 MPa shear force), and electrically reliable down to 2 K. This work pushes quantum computing to highly scaled-out densely integrated qubits with superconducting controls.
To realize the potential of quantum computing, a compact integrated system with millions of qubits and control electronics is required. Existing analog schemes are challenging for the compact system with a high I/O density and wiring requirement. In this paper, a new digital assembly scheme providing high-density I/O (>10000 per mm2) is proposed. Qubits can be heterogeneously integrated with digital superconducting control electronics on a System-on-Wafer Superconducting Silicon Interconnect Fabric which is experimentally validated in this work. The key potential advantages include nanoseconds of control/readout cycle, 10–4qubit error rate, 0.2 mW system power dissipation per qubit. The dies can be assembled on the SoW platform with ≤ 100 µm inter-dielet spacing through the Au interlayer technology, which is demonstrated to be fine pitch (≤10 um), quantum-compatible (30 MPa shear force), and electrically reliable down to 2 K. This work pushes quantum computing to highly scaled-out densely integrated qubits with superconducting controls.
For millions of qubits, I/O, wiring, control/readout signal latency, and thermal budget per qubit are challenging. A novel scheme adopting superconducting digital electronics integrated on a System-on-Wafer (SoW) Superconducting Silicon Interconnect Fabric is proposed. We demonstrate the SoW with a fine interconnect pitch <10 μm, (~60 μm) lateral inter-dielet spacing, and a low profile (≤ 1 μm) die-attach. The proposed design can attain a picosecond interconnect latency, a potential nanosecond qubit control latency, and a prospective 10000X reduction in power dissipation. This work is able to fulfill the true potential of quantum computing.
To preserve delicate quantum signals (few hundreds to a few tens of µV), low-loss and low-crosstalk inter-dielet communication is a must in a wafer-scale integrated quantum system using Superconducting-IF. In this paper, inter-dielet links (short: 125 μm and 500 μm; long: 1750 μm) with L/S (2/2 and 5/5 μm) are characterized in a broadband 20 GHz range through simulation and experiments at 4K A compact assembly (inter-dielet spacing of 100 μm) through the quantum-compatible fine-pitch (10 um) Au interlayer is conducted. For insertion loss and crosstalk characterization, the simulated and measured results are presented to be low-loss (<1 dB) and low-crosstalk (< -23 dB) in the broadband 20 GHz range with short (≤ 500 um) and long (1750 um) links and two L/S (2/2 and 5/5 um). It is one of the first 20 GHz broadband RF characterization of short superconducting links (≤ 500 um) through advanced packaging for cryogenic inter-dielet quantum communication. This work brings large-scale quantum computing closer to being realized through compact heterogeneous integration.
This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Abstract As superconducting qubit circuits become more complex, addressing a large array of qubits becomes a challenging engineering problem. Dense arrays of qubits benefit from, and may require, access via the third dimension to alleviate interconnect crowding. Through-silicon vias (TSVs) represent a promising approach to three-dimensional (3D) integration in superconducting qubit arrays—provided they are compact enough to support densely-packed qubit systems without compromising qubit performance or low-loss signal and control routing. In this work, we demonstrate the integration of superconducting, high-aspect ratio TSVs—10 μm wide by 20 μm long by 200 μm deep—with superconducting qubits. We utilize TSVs for baseband control and high-fidelity microwave readout of qubits using a two-chip, bump-bonded architecture. We also validate the fabrication of qubits directly upon the surface of a TSV-integrated chip. These key 3D-integration milestones pave the way for the control and readout of high-density superconducting qubit arrays using superconducting TSVs.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.
Quantum computers now encounter the significant challenge of scalability, similar to the issue that classical computing faced previously. Recent results in high-fidelity spin qubits manufactured with a Si CMOS technology, along with demonstrations that cryogenic CMOS-based control/readout electronics can be integrated into the same chip or die, opens up an opportunity to break out the challenges of qubit size, I/O, and integrability. However, the power consumption of cryogenic CMOS-based control/readout electronics cannot support thousands or millions of qubits. Here, we show that III–V two-dimensional electron gas and Nb superconductor-based cryogenic electronics can be integrated with Si and operate at extremely low power levels, enabling the control and readout for millions of qubits. Our devices offer a unity gain cutoff frequency of 601 GHz, a unity power gain cutoff frequency of 593 GHz, and a low noise indication factor (IDgm−1) of 0.21VmmS−1 at 4 K using more than 10 times less power consumption than CMOS. The power consumption of control/readout electronics remains a limiting factor for large-scale quantum computers. Here, the authors demonstrate III–V semiconductor and Nb superconductor-based cryogenic electronics integrated on silicon for large-scale quantum computing systems.