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International Symposium on Quality Electronic Design (ISQED)

Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric

Yu-Tao Yang, Subramanian S. Iyer

Published Apr 7, 2021• 1 citation
Publisher

Abstract

For millions of qubits, I/O, wiring, control/readout signal latency, and thermal budget per qubit are challenging. A novel scheme adopting superconducting digital electronics integrated on a System-on-Wafer (SoW) Superconducting Silicon Interconnect Fabric is proposed. We demonstrate the SoW with a fine interconnect pitch <10 μm, (~60 μm) lateral inter-dielet spacing, and a low profile (≤ 1 μm) die-attach. The proposed design can attain a picosecond interconnect latency, a potential nanosecond qubit control latency, and a prospective 10000X reduction in power dissipation. This work is able to fulfill the true potential of quantum computing.

DOI
10.1109/isqed51717.2021.9424295

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For millions of qubits, I/O, wiring, control/readout signal latency, and thermal budget per qubit are challenging. A novel scheme adopting superconducting digital electronics integrated on a System-on-Wafer (SoW) Superconducting Silicon Interconnect Fabric is proposed. We demonstrate the SoW with a fine interconnect pitch <10 μm, (~60 μm) lateral inter-dielet spacing, and a low profile (≤ 1 μm) die-attach. The proposed design can attain a picosecond interconnect latency, a potential nanosecond qubit control latency, and a prospective 10000X reduction in power dissipation. This work is able to fulfill the true potential of quantum computing.
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This work presents a conceptual architecture and technological roadmap for a scalable superconducting quantum computing platform based on modular design principles. Rather than introducing a new qubit technology, the proposal focuses on addressing critical engineering bottlenecks that currently limit the large-scale deployment of quantum processors, including wiring complexity, electromagnetic crosstalk, fabrication yield, and latency in error-correction feedback loops.The proposed framework introduces a modular hybrid architecture (“Quantum Mesh”), where medium-scale quantum chiplets containing 25–50 superconducting transmon qubits are interconnected through advanced 3D packaging and cryogenic infrastructure. This approach aims to improve manufacturing yield, reduce wiring density, and enable rack-level integration of quantum processing units while maintaining high gate fidelities and manageable thermal loads.A second central element of the proposal is the integration of a high-fidelity digital twin environment capable of simulating qubit dynamics, noise sources, control latency, and thermal constraints at nanosecond resolution. This predictive framework is intended to support hardware iteration cycles prior to fabrication, potentially accelerating design optimization and system validation.The document outlines a three-year development pathway targeting 100–200 physical qubits and several logical qubits using surface code error correction, followed by a longer-term scaling strategy toward quantum fabrics exceeding one thousand qubits. By combining modular quantum chiplets, partial cryogenic electronics, and predictive digital twin modeling, the proposed architecture explores a plausible industrial pathway toward large-scale quantum computing systems.
Quantum computers now encounter the significant challenge of scalability, similar to the issue that classical computing faced previously. Recent results in high-fidelity spin qubits manufactured with a Si CMOS technology, along with demonstrations that cryogenic CMOS-based control/readout electronics can be integrated into the same chip or die, opens up an opportunity to break out the challenges of qubit size, I/O, and integrability. However, the power consumption of cryogenic CMOS-based control/readout electronics cannot support thousands or millions of qubits. Here, we show that III–V two-dimensional electron gas and Nb superconductor-based cryogenic electronics can be integrated with Si and operate at extremely low power levels, enabling the control and readout for millions of qubits. Our devices offer a unity gain cutoff frequency of 601 GHz, a unity power gain cutoff frequency of 593 GHz, and a low noise indication factor (ID gm−1)\left(\sqrt{{I}_{{{\rm{D}}}}}\, {g}_{{{{\rm{m}}}}}^{-1}\right)(ID​​gm−1​) of 0.21VmmS−10.21\sqrt{{{{\rm{Vmm}}}}}\scriptstyle\sqrt{{S}^{-1}}0.21Vmm​S−1​ at 4 K using more than 10 times less power consumption than CMOS. The power consumption of control/readout electronics remains a limiting factor for large-scale quantum computers. Here, the authors demonstrate III–V semiconductor and Nb superconductor-based cryogenic electronics integrated on silicon for large-scale quantum computing systems.
Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and manufacturing processes. We present a wafer-scale packaging architecture supporting over 500 qubits on a single 3-inch die. The package is engineered to suppress parasitic RF modes, and to mitigate material loss through simulation-informed design while managing differential thermal contraction to ensure robust operation at millikelvin temperatures. System-level heat-load calculations from a large wiring payload show this package may be operated in commercial dilution refrigerators. Measurements of the qubits loaded into the package show median T1T_1T1​, T2e∼100 μT_{2e} \sim 100~μT2e​∼100 μs ($\sim$100 qubits) alongside readout with median fidelity of 97.5% (54 qubits) and a median qubit temperature of 36 mK (54 qubits). These results validate the performance of these packages and demonstrate that large-scale integration can be achieved without compromising device performance. Finally, we highlight the utility of these packages as a tool for high throughput feedback on qubit figures of merit over large sample sizes, allowing identification of performance outliers in the tails of the coherence distribution, a critical capability for informing fabrication and manufacture of high-quality quantum qubits and quantum processors.
Abstract To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al 0.995 Cu 0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.