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IEEE Transactions on Applied Superconductivity

Emerging Attacks on Logic Locking in SFQ Circuits and Related Countermeasures

Yerzhan Mustafa, Tahereh Jabbari, Selçuk Köse

Published Feb 16, 2022• 24 citations
Publisher

Abstract

Hardware security in single flux quantum (SFQ) circuits is an emerging research area due the increasing demand of data centers operating with sensitive information and the limited number of fabrication facilities, where certain stages can be compromised. An existing logic locking technique in SFQ circuits, that is based on supplying additional current with mutual inductance to change the circuit operation, is analyzed in this article. Two new attacks on this logic locking technique are proposed. In the first attack, the locked OR cell is reset by applying a specific input combination. As a result, the overall range of correct key values can be increased by approximately 18.8 and 32.9% depending on the location of the generated mutual inductance. In the second attack, an overproduction threat model is proposed, which significantly decreases the number of measurements needed to reveal the secret key from exponential to linear scale. As a case study, a 4-to-2 priority encoder optimized for SFQ applications is designed and logic locked. The proposed attack is performed on this locked design. Finally, potential countermeasures for each attack type are discussed with the corresponding tradeoffs.

DOI
10.1109/tasc.2022.3151881

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Hardware security in single flux quantum (SFQ) circuits is an emerging research area due the increasing demand of data centers operating with sensitive information and the limited number of fabrication facilities, where certain stages can be compromised. An existing logic locking technique in SFQ circuits, that is based on supplying additional current with mutual inductance to change the circuit operation, is analyzed in this article. Two new attacks on this logic locking technique are proposed. In the first attack, the locked OR cell is reset by applying a specific input combination. As a result, the overall range of correct key values can be increased by approximately 18.8 and 32.9% depending on the location of the generated mutual inductance. In the second attack, an overproduction threat model is proposed, which significantly decreases the number of measurements needed to reveal the secret key from exponential to linear scale. As a case study, a 4-to-2 priority encoder optimized for SFQ applications is designed and logic locked. The proposed attack is performed on this locked design. Finally, potential countermeasures for each attack type are discussed with the corresponding tradeoffs.
The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.
Single flux quantum (SFQ) technology is currently used as a cryogenic control and readout circuitry of superconducting quantum computers. The low power operation and high switching frequency of SFQ technology are instrumental to efficiently scale a quantum computer. With the growing interest in the hardware security of SFQ circuits, a novel side-channel leakage mechanism in SFQ-to-dc converters is uncovered in this article. The leakage mechanism is investigated for two logic styles, namely, rapid SFQ (RSFQ) and energy-efficient RSFQ (ERSFQ). By observing the fluctuations in the power supply provided by the room temperature electronics, a malicious adversary can extract critical information about the applied input signals. This type of side-channel leakage can lead to serious security vulnerabilities for superconducting electronics and quantum computers. Two potential side-channel attacks that exploit this vulnerability and target SFQ-based qubit control and readout systems are proposed.
With the growing interest in emerging and upcoming quantum computers, it is important to consider possible hardware security vulnerabilities and countermeasures. This work proposes side-channel attacks targeting classical-quantum interface circuits in superconducting quantum computers. Particularly, a single flux quantum (SFQ) technology-based classical controller, which is a promising candidate for large-scale in-fridge qubit control and readout circuitry, is considered. We have uncovered a substantial side-channel leakage from superconducting interface circuits through the power supply variations. An attacker, who has access to room temperature electronics where the power is generated, can successfully decode certain information about various components within quantum computers.
Single flux quantum (SFQ) technology has garnered significant attention due to its low switching power and high operational speed. Researchers have been actively pursuing more advanced devices and technologies to further reduce the reliance on inductors, bias, and dynamic power. Recently, innovative magnetic Josephson junction devices have emerged, enhancing the field of superconductor electronics logic. This article introduces a novel cell library design that relies entirely on Josephson junctions, showing promising potential for eliminating the need for inductors in conventional SFQ cells. This results in a 55% reduction in cell size and an 80% decrease in both static and dynamic power consumption. The proposed library implements a half flux quantum logic, where each pulse duration is half that of a SFQ pulse. This article presents the schematics of the basic cells, emphasizing critical circuit parameters and their margins. In addition, it examines layout blueprints, showcasing the advantageous area-saving characteristics of the proposed design.
I describe the fundamental technologies concerning the single flux quantum (SFQ) logic circuits. Recent remarkable progress in the computer-aided-design (CAD) tool, which is based on the cell-based design technique, enables us to make SFQ integrated circuits. Although the circuit demonstrated so far has 2, 300 Josephson junctions at most, this number will increase because the CAD tool is advancing. The on-chip test system has also been developed to test the high-speed nature of the SFQ circuit. For example, the shift-register employed as a circuit under test operates correctly at 55GHz. I also describe the potential applications of the SFQ circuits. An analog-to-digital converter utilizing the high-speed nature and high sensitivity in the SFQ circuits will be applicable to the front end of the future base stations, which require broad band width, high sensitivity, and flexibility. Packet switches used in the future high-end router need high throughput and functionality. Only SFQ-based packet switches can meet these requirements. Another potential application is a high-end server. We have studied micro-architectures of a processor executing the Java Byte Codes directly and a multiprocessor system constructed by connecting the processors and memories via the ultra-broad-band SFQ network switches. Throughout the study, we employ the concept of the complexity-reduction (CORE), in which the high-speed nature of the SFQ circuits is used for the reduction of the circuit scale or simplification of the micro-architecture; the multiprocessor system has high performances. These clear applications promote rapid technological progress in the SFQ technology, though we must make every endeavor to find new application fields.
High current requirements in single flux quantum (SFQ) circuits pose scalability challenges, contributing to issues such as high thermal loads, static power dissipation, and increased sensitivity to flux trapping under non-ideal shielding or cool down conditions. AC biasing, successfully used in other superconductive logic families, has been integrated into rapid single flux quantum (RSFQ) circuits and typically includes AC-to-DC converters, introducing area and complexity overhead. This work proposes an alternative method for applying AC biasing to existing RSFQ circuits using inductively coupled bias junctions, eliminating the need for AC-to-DC converters. This approach also combines resistive DC biasing with inductive AC biasing, reducing static power dissipation. The proposed approach targets clock splitters, which are significant contributors to on-chip current demand, achieving an average 94% reduction in splitter current and a 62% reduction in overall system current with a Josephson junction overhead of 6.5%. The technique is compatible with conventional RSFQ system architectures and logic families while significantly enhancing energy efficiency and scalability.