The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.
The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.
Hardware security in single flux quantum (SFQ) circuits is an emerging research area due the increasing demand of data centers operating with sensitive information and the limited number of fabrication facilities, where certain stages can be compromised. An existing logic locking technique in SFQ circuits, that is based on supplying additional current with mutual inductance to change the circuit operation, is analyzed in this article. Two new attacks on this logic locking technique are proposed. In the first attack, the locked OR cell is reset by applying a specific input combination. As a result, the overall range of correct key values can be increased by approximately 18.8 and 32.9% depending on the location of the generated mutual inductance. In the second attack, an overproduction threat model is proposed, which significantly decreases the number of measurements needed to reveal the secret key from exponential to linear scale. As a case study, a 4-to-2 priority encoder optimized for SFQ applications is designed and logic locked. The proposed attack is performed on this locked design. Finally, potential countermeasures for each attack type are discussed with the corresponding tradeoffs.
Design and manufacturing of superconductive electronics have been evolving over the past three decades with significant progress made in related fields. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconductive logic families and its energy-efficient variants (ERSFQ and eSFQ) have shown promise as an ultra lowpower and high-speed circuit fabric. SFQ circuits have been demonstrated at tens of GHz with an energy consumption of an attojoule per gate. There are many differences between SFQ and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. SFQ logic gates have no gain and hence splitters are needed to drive multiple fanouts. Design and successful demonstration of a controllable superconducting switch and a compact reliable memory element have evaded researchers so far. This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.
Single flux quantum (SFQ) technology is currently used as a cryogenic control and readout circuitry of superconducting quantum computers. The low power operation and high switching frequency of SFQ technology are instrumental to efficiently scale a quantum computer. With the growing interest in the hardware security of SFQ circuits, a novel side-channel leakage mechanism in SFQ-to-dc converters is uncovered in this article. The leakage mechanism is investigated for two logic styles, namely, rapid SFQ (RSFQ) and energy-efficient RSFQ (ERSFQ). By observing the fluctuations in the power supply provided by the room temperature electronics, a malicious adversary can extract critical information about the applied input signals. This type of side-channel leakage can lead to serious security vulnerabilities for superconducting electronics and quantum computers. Two potential side-channel attacks that exploit this vulnerability and target SFQ-based qubit control and readout systems are proposed.
Superconductive electronics is a promising candidate for supplementing or replacing existing CMOS VLSI systems. Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive technologies operating at tens of gigahertz while reducing the operating power by up to three orders of magnitude as compared to conventional semiconductor systems. Achieving VLSI complexity of RSFQ integrated systems, however remains an elusive task due to fundamental differences between RSFQ and CMOS technologies. Most RSFQ logic gates, such as NOT and XOR are sequential in nature. Compared to CMOS, the number of logical pipeline stages is prohibitively large, greatly complicating the design of complex systems. Furthermore, additional circuitry, such as splitters and path balancing flip flops, constitute a major overhead. In this paper, a gate compounding technique is presented to maximize the functionality achievable within a single clock cycle. The logic gates are decomposed into primitives that can be efficiently combined to evaluate complex expressions in a single clock cycle. Structures generated by gate compounding are not sensitive to signal arrival time, simplifying the system design process. The expressive power of SFQ logic is increased, allowing any two-input truth table to be implemented within a single clock cycle. A 4-bit carry lookahead adder (CLA) is implemented using compound gates, demonstrating smaller area, pipeline depth, and clock tree size.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, not requiring large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve the parameter margins.