Today there is a lot of advent in the digital electronics with different type of circuits using quantum technology. Different quantum gates can be designed and implemented for several combinational logic circuits such as multiplexers, Demultiplexer and ALU. These are the circuits used particularly in data processing and for data manipulation. The aim of paper is to implement half subtractor and full subtractor on quantum qiskit and IBM Quantum Experience interface.
Today there is a lot of advent in the digital electronics with different type of circuits using quantum technology. Different quantum gates can be designed and implemented for several combinational logic circuits such as multiplexers, Demultiplexer and ALU. These are the circuits used particularly in data processing and for data manipulation. The aim of paper is to implement half subtractor and full subtractor on quantum qiskit and IBM Quantum Experience interface.
The futuristic computing systems with low power dissipation are of interest among Researchers. Reversible logic provides less power dissipation as well as individual output assignment for each individual input. Hence designing reversible circuits are of great importance which finds significant application in Quantum Computing. It is a kind of computing that performs operations on data using quantum mechanical properties, such as superposition and entanglement. Unlike classical computing, quantum computing works on quantum bits. Qubits are processed by Quantum circuits, the basic building blocks of Quantum Computers. In this paper reversible Quantum arithmetic circuit like half adder, full adder, half subtractor and full subtractor are simulated using IBM Q simulator and the corresponding truth tables are verified.
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
Quantum Computing fast development is leading to the emergence of a wide variety of software development frameworks. In general, in these frameworks users can implement quantum algorithms and circuits, evaluating their behavior through simulations, and in some cases, executing them on Noisy Intermediate-Scale Quantum (NISQ) devices. IBM has been a pioneer in this field, providing public access to their devices through the IBM Q Experience Platform, using Python's open-source framework Qiskit. In this paper, we present the development of a n-bitstring half-adder and half-subtractor algorithm in Qiskit, analyzing the behavior on the IBM Q Experience simulator and real quantum processors.