The futuristic computing systems with low power dissipation are of interest among Researchers. Reversible logic provides less power dissipation as well as individual output assignment for each individual input. Hence designing reversible circuits are of great importance which finds significant application in Quantum Computing. It is a kind of computing that performs operations on data using quantum mechanical properties, such as superposition and entanglement. Unlike classical computing, quantum computing works on quantum bits. Qubits are processed by Quantum circuits, the basic building blocks of Quantum Computers. In this paper reversible Quantum arithmetic circuit like half adder, full adder, half subtractor and full subtractor are simulated using IBM Q simulator and the corresponding truth tables are verified.
The futuristic computing systems with low power dissipation are of interest among Researchers. Reversible logic provides less power dissipation as well as individual output assignment for each individual input. Hence designing reversible circuits are of great importance which finds significant application in Quantum Computing. It is a kind of computing that performs operations on data using quantum mechanical properties, such as superposition and entanglement. Unlike classical computing, quantum computing works on quantum bits. Qubits are processed by Quantum circuits, the basic building blocks of Quantum Computers. In this paper reversible Quantum arithmetic circuit like half adder, full adder, half subtractor and full subtractor are simulated using IBM Q simulator and the corresponding truth tables are verified.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Quantum computing represents a paradigm shift in computation by leveraging the principles of quantum mechanics such as superposition, entanglement, and interference to perform operations beyond classical limitations. Unlike classical computing systems that rely on irreversible logic operations and suffer from energy dissipation due to information loss, quantum systems utilize reversible unitary transformations that preserve information and improve computational efficiency. This paper presents a comprehensive framework for the design, simulation, and validation of quantum gates and reversible arithmetic circuits, including half adders and half subtractors. The proposed approach systematically maps classical arithmetic logic into quantum circuits using fundamental quantum gates such as Pauli-X, Hadamard, Controlled-NOT (CNOT), and Toffoli gates. The circuits are implemented and simulated using the Qiskit Aer framework, enabling detailed analysis of quantum state evolution and measurement outputs. The results obtained from simulation include program-level outputs, state vector representations, measurement counts, and probability distributions, all of which demonstrate strong agreement with classical truth tables. The analysis confirms the correctness, reversibility, and scalability of the proposed designs. Furthermore, a comparative performance evaluation highlights the advantages of quantum computing over classical approaches in terms of parallelism and energy efficiency. The proposed framework establishes a robust foundation for future implementation of complex Boolean logic and arithmetic operations in quantum systems.
Quantum computing is an emerging computational paradigm that represents and processes information using quantum states. This paper presents the implementation and simulation of a Quantum Half Adder using the IBM Qiskit framework. The proposed circuit performs one-bit binary addition and produces two outputs, SUM and CARRY, through reversible quantum operations. Classical input values are encoded into quantum states using Pauli-X gates. Controlled-NOT (CNOT) gates are used to realize the XOR relationship required for SUM generation, while a Toffoli (CCNOT) gate realizes the AND relationship required for CARRY generation. The complete design is implemented in Python and executed using the Qiskit Aer Simulator. Four possible input combinations are evaluated and the measured outputs are compared with the expected Half Adder truth table. Circuit visualization, terminal output, and measurement histograms are used to verify the operation. The results show that the simulated circuit produces the expected SUM and CARRY values for all input combinations. The work provides a simple practical model for understanding reversible quantum computation, quantum gates, and Qiskit-based quantum circuit simulation.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.