IEEE Computer Society Annual Symposium on VLSI

Automated Flag Qubit Insertion for Reliable Quantum Circuit Output

Nikita Acharya, Samah Mohamed Saeed

Published Jul 1, 2021• 4 citations

Abstract

Quantum circuit compilers play an important role in mitigating errors of quantum circuits executed on Noisy Intermediate-Scale Quantum (NISQ) computers. The compiler maps the quantum algorithm into a physical quantum circuit that satisfies the physical constraints of NISQ architecture. However, the reliability of NISQ computers is still very challenging. In this work, we design a new class of quantum test circuits using flag qubits based on error propagation. Furthermore, we automate the test point insertion. Our approach can detect errors at different points in the circuit to assess its output reliability. The goal is to select a qubit allocation that improves the quantum circuit output fidelity. We show the effectiveness of our approach using an IBM quantum computer and a noisy simulator.

DOI: 10.1109/isvlsi51109.2021.00085

Related papers

Test Points for Online Monitoring of Quantum Circuits

Nikita Acharya, Miroslav Urbánek, Wibe Albert de Jong +1 more

Noisy Intermediate-Scale Quantum (NISQ) computers consisting of tens of inherently noisy quantum bits (qubits) suffer from reliability problems. Qubits and their gates are susceptible to various types of errors. Due to limited numbers of qubits and high error rates, quantum error correction cannot be applied. Physical constraints of quantum hardware including the error rates are used to guide the design and the layout of quantum circuits. The error rates determine the selection of qubits and their operations. The resulting circuit is executed on the quantum computer. This study explores the risk of unexpected changes in the error rates of NISQ computers post-calibration. We show that unexpected changes in error rates can alter the output state of a quantum circuit. To detect these changes, we propose the insertion of test points into the quantum circuit to enable online monitoring of the physical qubit behavior. We utilize classical, superposition, and uncompute test points. Furthermore, we use a gate error coverage metric to assess the quality of the tests. We verify the effectiveness of the proposed scheme on different IBM quantum computers (IBM Q), in addition to a noisy simulation that shows the scalability of the proposed approach.

ACM Journal on Emerging Technologies in Computing SystemsOct 22, 20217 citations

Machine-Learning-Based Qubit Allocation for Error Reduction in Quantum Circuits

Travis LeCompte, Fang Qi, Xu Yuan +3 more

Quantum computing is a quickly growing field with great potential for future technology. Quantum computers in the current noisy intermediate-scale quantum (NISQ) era face two major limitations - qubit count and error vulnerability. Although quantum error correction (QEC) methods exist, they are not applicable to the current size of computers, requiring thousands of qubits, while current NISQ systems have hundreds at most. It is therefore imperative to improve the reliability of the circuits as much as possible to make them robust to the errors that will occur. One common approach is to adjust the compilation process of a circuit to create a final circuit with improved reliability. However, there are many decisions to be made when compiling that affect the final performance of the circuit, two of the most critical ones being the mapping of logical to physical qubits (the qubit allocation problem) and the movement of qubits to satisfy two-qubit gate adjacency requirements (the qubit routing problem). We focus on solving the qubit allocation problem and identifying initial layouts that reduce error. To identify these layouts, we combine reinforcement learning with a graph neural network (GNN)-based Q-network for analyzing both the connections and error rates of the graph-like backend of superconducting quantum computers to make mapping decisions, creating a Graph Neural Network Assisted Compilation (GNAQC) strategy. We provide both the circuit and the properties of the target backend as input to guide the decision-making process. We work with the IBM Qiskit API to compile and simulate our quantum circuits. We train the architecture using a set of four backends and six circuits and find that GNAQC generally outperforms pre-existing qubit allocation algorithms, increasing final relative output fidelity by roughly 12.7%.

IEEE Transactions on Quantum EngineeringJan 1, 202321 citations

Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output

Vedika Saravanan, Samah Mohamed Saeed

While current quantum computers, referred to as Noisy Intermediate-Scale Quantum (NISQ) computers, are expected to be beneficial for different applications, they are prone to different types of errors. In order to enhance the reliability of quantum systems, noise-aware quantum compilers are used to generate physical quantum circuits to be executed on NISQ computers. The quantum hardware is calibrated very frequently and its error rates are computed accordingly. Based on the hardware error rates, a quantum compiler allocates physical qubits and schedules quantum operations. However, error rates may change post-calibration. To incorporate dynamic error rates into quantum circuit compilation with minimum cost, we propose a Machine Learning (ML)-based scheme to detect the incorrect output of the quantum circuit and predict the Probability of Successful Trials (PST) with high accuracy. Our approach can verify the error rates of the quantum hardware and validate the correctness of the extracted quantum circuit output. We provide a case study of our ML-based reliability models using IBM Q16 Melbourne quantum computer. Our results show that the proposed scheme achieves a very high prediction accuracy.

IEEE European Test Symposium (ETS)May 24, 20219 citations

A lightweight approach to detect malicious/unexpected changes in the error rates of NISQ computers

Nikita Acharya, Samah Mohamed Saeed

Despite the current progress in quantum computing, the reliability of quantum computers is very challenging. Near-term quantum computers referred to as Noisy Intermediate-Scale Quantum (NISQ) computers are expected to operate in the presence of errors. To run a quantum circuit on a NISQ computer, the circuit should be mapped to satisfy the physical constraints of the quantum architecture. The mapping process takes into account the error rates of the quantum hardware. It selects physical qubits and their movements, which minimize the circuit error rates. The output of the quantum circuit can be obtained through several runs on NISQ computers.

Nov 2, 202026 citations

Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation

Vedika Saravanan, Samah Mohamed Saeed

Noisy Intermediate-Scale Quantum (NISQ) algorithms, which run on noisy quantum computers should be carefully designed to boost the output state fidelity. While several compilation approaches have been proposed to minimize circuit errors, they often omit the detailed circuit structure information that does not affect the circuit depth or the gate count. In the presence of spatial variation in the error rate of the quantum gates, adjusting the circuit structure can play a major role in mitigating errors. In this paper, we exploit the freedom of gate reordering based on the commutation rules to show the impact of gate error propagation paths on the output state fidelity of the quantum circuit, propose advanced predictive techniques to project the success rate of the circuit, and develop a new compilation phase post-quantum circuit mapping to improve its reliability. Our proposed approaches have been validated using a variety of quantum circuits with different success metrics, which are executed on IBM quantum computers. Our results show that rescheduling quantum gates based on their error propagation paths can significantly improve the fidelity of the quantum circuit in the presence of variable gate error rates.

arXiv:2201.12946Jan 31, 20221 citation

Error-Resilient Quantum Compiler Design for Efficient Qubit Mapping, Gate Optimization, and Noise Mitigation in NISQ-Era Devices,

Beyza Altan

The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.

Next generation.Feb 20, 20260 citations