Despite the current progress in quantum computing, the reliability of quantum computers is very challenging. Near-term quantum computers referred to as Noisy Intermediate-Scale Quantum (NISQ) computers are expected to operate in the presence of errors. To run a quantum circuit on a NISQ computer, the circuit should be mapped to satisfy the physical constraints of the quantum architecture. The mapping process takes into account the error rates of the quantum hardware. It selects physical qubits and their movements, which minimize the circuit error rates. The output of the quantum circuit can be obtained through several runs on NISQ computers.
Despite the current progress in quantum computing, the reliability of quantum computers is very challenging. Near-term quantum computers referred to as Noisy Intermediate-Scale Quantum (NISQ) computers are expected to operate in the presence of errors. To run a quantum circuit on a NISQ computer, the circuit should be mapped to satisfy the physical constraints of the quantum architecture. The mapping process takes into account the error rates of the quantum hardware. It selects physical qubits and their movements, which minimize the circuit error rates. The output of the quantum circuit can be obtained through several runs on NISQ computers.
Noisy Intermediate-Scale Quantum (NISQ) computers consisting of tens of inherently noisy quantum bits (qubits) suffer from reliability problems. Qubits and their gates are susceptible to various types of errors. Due to limited numbers of qubits and high error rates, quantum error correction cannot be applied. Physical constraints of quantum hardware including the error rates are used to guide the design and the layout of quantum circuits. The error rates determine the selection of qubits and their operations. The resulting circuit is executed on the quantum computer. This study explores the risk of unexpected changes in the error rates of NISQ computers post-calibration. We show that unexpected changes in error rates can alter the output state of a quantum circuit. To detect these changes, we propose the insertion of test points into the quantum circuit to enable online monitoring of the physical qubit behavior. We utilize classical, superposition, and uncompute test points. Furthermore, we use a gate error coverage metric to assess the quality of the tests. We verify the effectiveness of the proposed scheme on different IBM quantum computers (IBM Q), in addition to a noisy simulation that shows the scalability of the proposed approach.
Quantum computing in the Noisy Intermediate-Scale Quantum (NISQ) era faces significant challenges due to the limitations in quantum gate fidelity and elevated error rates, which impede the successful execution of large-scale quantum circuits. One major source of errors in quantum computing is ’coherence errors’, which arise from the idle time during circuit execution. Specifically, factors such as uneven gate operations, hardware limitations, and qubit connectivity constraints collectively contribute to the formation of ’holes’ in quantum circuits, leading to ’idle qubits’. These idle periods, in turn, increase noise and error rates, thus negatively impacting the overall reliability of quantum circuits’ outputs.
Noisy intermediate scale quantum (NISQ) computers are becoming a reality thanks to the recent advances made by researchers who physically build such systems. In order to execute corresponding quantum algorithms (usually provided in terms of quantum circuits), certain physical constraints in the architectures need to be satisfied. More precisely, physical constraints restrict the possible interactions between qubits which frequently result in cases where qubits which are supposed to interact in a quantum circuit are not allowed to interact on the physical device. Thus far, this is addressed by dedicated methods that map the logical quantum circuit to a physical realization and satisfy the constraints by inserting further operations. This leads to additional costs which harm the fidelity of the circuit and, hence, urgently need to be avoided. Unfortunately, current state-of-the-art approaches for this mapping process take the existing architectures as invariant and only try to reduce the number of additionally needed operations. In contrast, (slight) changes in the, respectively, given architectures (which still keep the underlying physical constraints satisfied) might be possible and may allow for even better (i.e., less costly) mappings. But this potential has not been investigated yet. In this work, we explore this potential. More precisely, we introduce several schemes for generating alternative coupling graphs (and, by this, quantum computing architectures) that still might be able to satisfy physical constraints but, at the same time, allow for a more efficient realization of the desired quantum functionality. Evaluations confirm the potential of those alternative coupling graphs and demonstrate that they can reduce the mapping overhead by up to 60% in the best case and up to almost 40% on average.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
Near-term quantum computers do not have the ability to perform error correction. Such Noisy Intermediate Scale Quantum (NISQ) computers can produce incorrect output as the computation is subjected to errors. The applications on a NISQ machine try to infer the correct output by running the same program thousands of times and logging the output. If the error rates are low and the errors are not correlated, then the correct answer can be inferred as the one appearing with the highest frequency. Unfortunately, quantum computers are subjected to correlated errors, which can cause an incorrect answer to appear more frequently than the correct answer.
The pace of innovation in quantum information science has recently exploded due to the hope that a quantum computer will be able to solve a multitude of problems that are intractable using classical hardware. Current quantum devices are in what has been termed the ``noisy intermediate-scale quantum'', or NISQ stage. Quantum hardware available today with 50-100 physical qubits may be among the first to demonstrate a quantum advantage. However, there are many challenges to overcome, such as dealing with noise, lowering error rates, improving coherence times, and scalability. \n \nWe are at a time in the field where minimization of resources is critical so that we can run our algorithms sooner rather than later. Running quantum algorithms ``at scale'' incurs a massive amount of resources, from the number of qubits required to the circuit depth. A large amount of this is due to the need to implement operations fault-tolerantly using error-correcting codes. \n \nFor one, to run an algorithm we must be able to efficiently read in and output data. Fault-tolerantly implementing quantum memories may become an input bottleneck for quantum algorithms, including many which would otherwise yield massive improvements in algorithm complexity. We will also need efficient methods for tomography to characterize and verify our processes and outputs. Researchers will require tools to automate the design of large quantum algorithms, to compile, optimize, and verify their circuits, and to do so in a way that minimizes operations that are expensive in a fault-tolerant setting. Finally, we will also need overarching frameworks to characterize the resource requirements themselves. Such tools must be easily adaptable to new developments in the field, and allow users to explore tradeoffs between their parameters of interest. \n \nThis thesis contains three contributions to this effort: improving circuit synthesis using large-scale parallelization; designing circuits for quantum random-access memories and analyzing various time/space tradeoffs; using the mathematical structure of discrete phase space to select subsets of tomographic measurements. For each topic the theoretical work is supplemented by a software package intended to allow others researchers to easily verify, use, and expand upon the techniques herein.