Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.
Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.
Quantum computing is gaining momentum in revolutionizing the way we approach complex problem-solving. However, the practical implementation of quantum algorithms remains a significant challenge due to the error-prone and hardware limits of near-term quantum devices. For instance, physical qubit connections are limited, which necessitates the use of quantum SWAP gates to dynamically transform the logical topology during execution. In addition, to optimize fidelity, it is essential to ensure that 1) the allocated hardware has a low error rate and 2) the number of SWAP gates injected into the circuit is minimized. To address these challenges, we propose a suite of algorithms: the Fidelity-aware Graph Extraction Algorithm (FGEA) is used to identify the hardware region with the lowest probability of error, the Frequency-based Mapping Algorithm (FMA) allocates logical-physical qubits that reduce the potential distance of topological transformation, and the Heuristic Routing Algorithm (HRA) searches for an optimal swapping injection strategy. We evaluate the proposed algorithms on the IBM-provided Noisy Intermediate-Scale Quantum (NISQ) computer, using a dataset consisting of 17 different quantum circuits of various sizes. The circuits are executed on the IBM Toronto Falcon processor. The three proposed algorithms outperform the existing SABRE algorithm in reducing the number of SWAP gates required. Therefore, our proposed algorithms hold significant promise in enhancing the fidelity and reducing the number of SWAP gates required in implementing Quantum algorithms.
Abstract Quantum compilation bridges the gap between abstract quantum algorithms and physical hardware execution. However, on Noisy Intermediate-Scale Quantum (NISQ) devices, particularly within superconducting architectures, mapping logical circuits to physical qubits remains a fundamental bottleneck due to rigid connectivity constraints and heterogeneous noise profiles. While exact mapping solvers theoretically ensure optimality, they face severe scalability issues on large-scale chips. The search space for global optimization becomes intractable as the system size increases. This scalability barrier largely arises because conventional methods often treat the hardware coupling graph as a homogeneous entity. By performing global searches with weak awareness of physical fidelity distributions, they fail to exploit the hardware’s inherent structural advantages. To address this, we propose HAQA, a hardware-guided strategy that shifts the mapping paradigm from a blind global search to an adaptive, fidelity-aware regional optimization. Specifically, HAQA identifies optimal topological subgraphs through a community-based recursive fusion mechanism. This approach achieves a dual benefit: it reduces solving complexity from exponential to polynomial levels by effectively pruning the search space, while simultaneously enhancing execution fidelity by prioritizing high-quality physical qubits. Experimental evaluations on IBM Eagle and Heron processors demonstrate significant efficiency gains. HAQA accelerates state-of-the-art SMT solvers (QSynth-v2 and TB-OLSQ2) by factors of 632.76× and 286.87×, respectively, while improving fidelity by up to 238.28%. These results suggest that integrating fine-grained physical awareness provides an effective pathway to balance computational complexity and execution quality in quantum compilation, positioning HAQA as a plug-and-play enhancement compatible with various solvers.
In the past few years, several quantum computers realized by the noisy intermediate-scale quantum (NISQ) technology have been released. However, there exists a significant limitation to using such computers, i.e., the connectivity constraint between physical qubits. To perform a 2-qubit quantum operation on such NISQ computers, its two logical qubits have to be mapped to a pair of physical qubits that satisfy the connectivity constraint. This mapping procedure requires additional operations to be introduced into the original quantum circuit, reducing its fidelity. Therefore, it is of great significance to design an algorithm that is able to complete the mapping task with minimal additional operations. In this article, we propose an efficient algorithm to solve this problem. Our algorithm consists of two core components, an expansion-from-center scheme to determine the initial mapping and a SWAP-based heuristic search algorithm to update the mapping. We introduce the maximum consecutive positive effect of a SWAP operation as the heuristic cost function, allowing our search algorithm to look ahead dynamically. Our algorithm is evaluated on IBM Q 20. The experimental results show that our algorithm can complete the mapping task in a very short time even for large-scale benchmarks with hundreds of thousands of operations, and outperforms the state-of-the-art in terms of the number of additional operations for most benchmarks considered.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Abstract Current quantum computers are noisy intermediate-scale quantum (NISQ) devices. Execution of quantum algorithms, represented as quantum circuits in the quantum circuit model, on such hardware requires transformation of the original circuits to comply with the hardware’s physical constraints, a process known as transpilation. One of the main constraints is limited qubit connectivity. In this work, we present an algorithm that transforms a quantum hashing circuit to satisfy architectural connectivity constraints while minimizing the number of CNOT gates (CNOT cost). The considered algorithm constructs a mapping from logical qubits to physical qubits that minimizes the CNOT cost of the resulting circuit. We optimize circuits for IBM Quantum devices.
Computationally expensive applications, including machine learning, chemical simulations, and financial modeling, are promising candidates for noisy intermediate scale quantum (NISQ) computers. In these problems, one important challenge is mapping a quantum circuit onto NISQ hardware while satisfying physical constraints of an underlying quantum architecture. Quantum circuit compilation (QCC) aims to generate feasible mappings such that a quantum circuit can be executed in a given hardware platform with acceptable confidence in outcomes. Physical constraints of a NISQ computer change frequently, requiring QCC process to be repeated often. When a circuit cannot directly be executed on a quantum hardware due to its physical limitations, it is necessary to modify the circuit by adding new quantum gates and auxiliary qubits, increasing its space and time complexity. An inefficient QCC may significantly increase error rate and circuit latency for even the simplest algorithms. In this article, we present artificial intelligence (AI)-based and heuristic-based methods recently reported in the literature that attempt to address these QCC challenges. We group them based on underlying techniques that they implement, such as AI algorithms including genetic algorithms, genetic programming, ant colony optimization and AI planning, and heuristics methods employing greedy algorithms, satisfiability problem solvers, dynamic, and graph optimization techniques. We discuss performance of each QCC technique and evaluate its potential limitations.