Abstract Quantum compilation bridges the gap between abstract quantum algorithms and physical hardware execution. However, on Noisy Intermediate-Scale Quantum (NISQ) devices, particularly within superconducting architectures, mapping logical circuits to physical qubits remains a fundamental bottleneck due to rigid connectivity constraints and heterogeneous noise profiles. While exact mapping solvers theoretically ensure optimality, they face severe scalability issues on large-scale chips. The search space for global optimization becomes intractable as the system size increases. This scalability barrier largely arises because conventional methods often treat the hardware coupling graph as a homogeneous entity. By performing global searches with weak awareness of physical fidelity distributions, they fail to exploit the hardware’s inherent structural advantages. To address this, we propose HAQA, a hardware-guided strategy that shifts the mapping paradigm from a blind global search to an adaptive, fidelity-aware regional optimization. Specifically, HAQA identifies optimal topological subgraphs through a community-based recursive fusion mechanism. This approach achieves a dual benefit: it reduces solving complexity from exponential to polynomial levels by effectively pruning the search space, while simultaneously enhancing execution fidelity by prioritizing high-quality physical qubits. Experimental evaluations on IBM Eagle and Heron processors demonstrate significant efficiency gains. HAQA accelerates state-of-the-art SMT solvers (QSynth-v2 and TB-OLSQ2) by factors of 632.76× and 286.87×, respectively, while improving fidelity by up to 238.28%. These results suggest that integrating fine-grained physical awareness provides an effective pathway to balance computational complexity and execution quality in quantum compilation, positioning HAQA as a plug-and-play enhancement compatible with various solvers.
Abstract Quantum compilation bridges the gap between abstract quantum algorithms and physical hardware execution. However, on Noisy Intermediate-Scale Quantum (NISQ) devices, particularly within superconducting architectures, mapping logical circuits to physical qubits remains a fundamental bottleneck due to rigid connectivity constraints and heterogeneous noise profiles. While exact mapping solvers theoretically ensure optimality, they face severe scalability issues on large-scale chips. The search space for global optimization becomes intractable as the system size increases. This scalability barrier largely arises because conventional methods often treat the hardware coupling graph as a homogeneous entity. By performing global searches with weak awareness of physical fidelity distributions, they fail to exploit the hardware’s inherent structural advantages. To address this, we propose HAQA, a hardware-guided strategy that shifts the mapping paradigm from a blind global search to an adaptive, fidelity-aware regional optimization. Specifically, HAQA identifies optimal topological subgraphs through a community-based recursive fusion mechanism. This approach achieves a dual benefit: it reduces solving complexity from exponential to polynomial levels by effectively pruning the search space, while simultaneously enhancing execution fidelity by prioritizing high-quality physical qubits. Experimental evaluations on IBM Eagle and Heron processors demonstrate significant efficiency gains. HAQA accelerates state-of-the-art SMT solvers (QSynth-v2 and TB-OLSQ2) by factors of 632.76× and 286.87×, respectively, while improving fidelity by up to 238.28%. These results suggest that integrating fine-grained physical awareness provides an effective pathway to balance computational complexity and execution quality in quantum compilation, positioning HAQA as a plug-and-play enhancement compatible with various solvers.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
Quantum computing is gaining momentum in revolutionizing the way we approach complex problem-solving. However, the practical implementation of quantum algorithms remains a significant challenge due to the error-prone and hardware limits of near-term quantum devices. For instance, physical qubit connections are limited, which necessitates the use of quantum SWAP gates to dynamically transform the logical topology during execution. In addition, to optimize fidelity, it is essential to ensure that 1) the allocated hardware has a low error rate and 2) the number of SWAP gates injected into the circuit is minimized. To address these challenges, we propose a suite of algorithms: the Fidelity-aware Graph Extraction Algorithm (FGEA) is used to identify the hardware region with the lowest probability of error, the Frequency-based Mapping Algorithm (FMA) allocates logical-physical qubits that reduce the potential distance of topological transformation, and the Heuristic Routing Algorithm (HRA) searches for an optimal swapping injection strategy. We evaluate the proposed algorithms on the IBM-provided Noisy Intermediate-Scale Quantum (NISQ) computer, using a dataset consisting of 17 different quantum circuits of various sizes. The circuits are executed on the IBM Toronto Falcon processor. The three proposed algorithms outperform the existing SABRE algorithm in reducing the number of SWAP gates required. Therefore, our proposed algorithms hold significant promise in enhancing the fidelity and reducing the number of SWAP gates required in implementing Quantum algorithms.
A massive gap exists between current quantum computing (QC) prototypes, and the size and scale required for many proposed QC algorithms. Current QC implementations are prone to noise and variability which affect their reliability, and yet with less than 80 quantum bits (qubits) total, they are too resource-constrained to implement error correction. The term Noisy Intermediate-Scale Quantum (NISQ) refers to these current and near-term systems of 1000 qubits or less. Given NISQ's severe resource constraints, low reliability, and high variability in physical characteristics such as coherence time or error rates, it is of pressing importance to map computations onto them in ways that use resources efficiently and maximize the likelihood of successful runs. This paper proposes and evaluates backend compiler approaches to map and optimize high-level QC programs to execute with high reliability on NISQ systems with diverse hardware characteristics. Our techniques all start from an LLVM intermediate representation of the quantum program (such as would be generated from high-level QC languages like Scaffold) and generate QC executables runnable on the IBM Q public QC machine. We then use this framework to implement and evaluate several optimal and heuristic mapping methods. These methods vary in how they account for the availability of dynamic machine calibration data, the relative importance of various noise parameters, the different possible routing strategies, and the relative importance of compile-time scalability versus runtime success. Using real-system measurements, we show that fine grained spatial and temporal variations in hardware parameters can be exploited to obtain an average 2.9x (and up to 18x) improvement in program success rate over the industry standard IBM Qiskit compiler. Despite small qubit counts, NISQ systems will soon be large enough to demonstrate "quantum supremacy", i.e., an advantage over classical computing. Tools like ours provide significant improvements in program reliability and execution time, and offer high leverage in accelerating progress towards quantum supremacy.
Due to several physical limitations in the realization of quantum hardware, today's quantum computers are qualified as noisy intermediate-scale quantum (NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50 to a few hundred) and noisy operations. Moreover, current realizations of superconducting quantum chips do not have the ideal all-to-all connectivity between qubits but rather at most a nearest-neighbor connectivity. All these hardware restrictions add supplementary low-level requirements. They need to be addressed before submitting the quantum circuit to an actual chip. Satisfying these requirements is a tedious task for the programmer. Instead, the task of adapting the quantum circuit to a given hardware is left to the compiler. In this article, we propose a hardware-aware (HA) mapping transition algorithm that takes the calibration data into account with the aim to improve the overall fidelity of the circuit. Evaluation results on IBM quantum hardware show that our HA approach can outperform the state of the art, both in terms of the number of additional gates and circuit fidelity.
Traditional compiler optimization focuses on maximizing performance within the constraints of classical architectures. However, quantum computing presents a fundamentally different paradigm, demanding a new approach to software optimization. This paper proposes a hardware-aware compiler optimization technique, inspired by quantum computing principles, to bridge the gap between high-level programming languages and the specific characteristics of quantum hardware. The core idea is to translate high-level code into quantum circuits while explicitly considering factors like qubit connectivity, gate fidelity, and decoherence. This approach allows for optimization strategies tailored to the unique limitations and opportunities of quantum devices, potentially leading to significant performance improvements compared to generic quantum compilation methods. The compiler operates by analyzing the algorithmic complexity, identifying quantum-native operations, and strategically mapping them onto the available quantum hardware, thereby minimizing the impact of hardware constraints. This paper outlines the framework, key components, and potential optimizations within this hardware-aware compiler.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.