Superconducting coplanar-waveguide (CPW) resonators are one of the key devices in circuit quantum electrodynamics (cQED). Their performance can be limited by dielectric losses in the substrate and in the material interfaces. Reliable modeling is required to aid in the design of low-loss CPW structures for cQED. We analyze the geometric dependence of the dielectric losses in CPW structures using finite-element modeling of the participation ratios of the lossy regions. In a practical scenario, uncertainties in the the dielectric constants and loss tangents of these regions introduce uncertainties in the theoretically predicted participation ratios. We present a method for combining loss simulations with measurements of two-level-system-limited quality factors and resonance frequencies of CPW resonators. Namely, we solve an inverse problem to find model parameters producing the measured values. High quality factors are obtainable by properly designing the cross-sectional geometries of the CPW structures, but more accurate modeling and design methods for low-loss CPW resonators are called for major future improvements. Our nonlinear optimization methodology for solving the aforementioned inverse problem is a step in this direction.
Superconducting quantum circuits are a leading candidate technology for large-scale quantum computing and simulation. Future scaling and improvements in device performance hinge upon a more detailed understanding of the sources of dielectric loss in these systems, yet standard techniques cannot separate the contributions from distinct dielectric regions to the aggregate device performance. This study presents a method for assessing the separate loss contributions from each material interface and bulk dielectric within such a circuit, enabling targeted improvements in performance by both informing device design and providing feedback to assess microfabrication techniques.
Material losses in superconducting circuits fundamentally limit qubit coherence times and resonator quality factors. Most research efforts focus on mitigating losses at circuit interfaces, including metal--substrate, substrate--air, and metal--air interfaces. However, the correlation between TLS and non-TLS losses with the intrinsic properties of the superconducting metal and the dielectric edge smoothness is not well studied. In this work, we link the aluminum film grain size to non-TLS losses and the dielectric trimming profile and roughness to TLS loss; both loss mechanisms are subsequently mitigated. To reduce metal-related losses, we engineer the aluminum microstructure by heating during deposition, increasing grain size and reducing grain boundary density. Beyond mitigating metal losses, we introduce a two-step etching technique, Tropic etching, to suppress dielectric TLS loss by producing an ultra-smooth silicon surface with minimal defects and redeposition. These results lay out the fabrication pathway for aluminum resonators with lower loss, demonstrating two-orders-of-magnitude improvement in quality factor from
6×104 to
2.3×106. Since aluminum is the basis for most high-coherence Josephson junctions and dielectric edges are inherent to all common device geometries, the improvements in aluminum microstructure and edge profiling, presented here, can enhance the performance of superconducting quantum devices.
We study the energy relaxation times (T1) of superconducting transmon qubits in 3D cavities as a function of dielectric participation ratios of material surfaces. This surface participation ratio, representing the fraction of electric field energy stored in a dissipative surface layer, is computed by a two-step finite-element simulation and experimentally varied by qubit geometry. With a clean electromagnetic environment and suppressed non-equilibrium quasiparticle density, we find an approximately proportional relation between the transmon relaxation rates and surface participation ratios. These results suggest dielectric dissipation arising from material interfaces is the major limiting factor for the T1 of transmons in 3D circuit quantum electrodynamics architecture. Our analysis also supports the notion of spatial discreteness of surface dielectric dissipation.