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Bulletin of the American Physical Society

Considerations for incorporating small logical qubits in digital error correction codes

David Rodríguez Pérez, Eliot Kapit

Published Mar 4, 2020• 0 citations
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Related papers

Passive Error Correction and Gates for a Very Small Logical Qubit

Eliot Kapit

Bulletin of the American Physical Society•Mar 16, 2017•0 citations

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

Eliot Kapit

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

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Robust hybrid qubit plane architecture for enhancing lattice-surgery-based surface codes

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Quantum computing offers unprecedented speed and power for solving complex problems, but its susceptibility to errors makes error-correction codes crucial. An important metric for evaluating the performance of error-correction codes is the code distance, which measures the number of errors a code can correct. Current qubit-plane architectures are implemented using the same code distance. However, a larger code distance reduces the logical error rate but increases resources. In fact, distance-5 code uses more resources but offers higher resilience to logical errors compared to distance-3 code. We propose a qubit-plane architecture for rotated and unrotated surface codes called Qentaurus that combines various code distances of logical qubits for robust error correction while maintaining qubit efficiency. Qentaurus is designed to be highly scalable regarding computation, layout, and code distance. We performed a case study using Qentaurus with distance-3 and -7 codes to evaluate the performance. Moreover, we additionally developed a qubit placement scheme that considers the critical path of the quantum circuit to reduce the logical error rate and gate count. Our main experimental results demonstrated that Qentaurus considerably reduces the overall logical error rate (by 15.76% on average and up to 25.25%) than that of the Distance-3 Checkerboard architecture. After additionally implementing the qubit placement scheme, the average reduction increases to 13.44% (up to 39.07%). Notably, the Qentaurus-37 maintains logical error rates comparable to those of the Distance-5 Checkerboard, achieving considerable qubit efficiency. The Distance-5 Checkerboard demands 227.7% more physical qubits than that required by the Distance-3 Checkerboard, while Qentaurus-37 utilizes just 131.2% of the physical qubits required by Distance-3 the Checkerboard, marking a substantial reduction of 96.5% in the resource gap. The overall gate count is reduced by an average of 1.74% with Qentaurus alone and by 3.33% on average with the qubit placement scheme. We believe that the proposed Qentaurus and qubit placement scheme have the potential to significantly improve the error-correction performance of large-scale quantum computers in practical applications.

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Logical error rates in the quantum error correction using small number of ancilla qubits

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Density-Matrix Simulation of Logical Qubit using 3-qubit Quantum Error Correction Code

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Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.

arXiv:1810.01029•Oct 2, 2018•0 citations
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Quantum computing offers unprecedented speed and power for solving complex problems, but its susceptibility to errors makes error-correction codes crucial. An important metric for evaluating the performance of error-correction codes is the code distance, which measures the number of errors a code can correct. Current qubit-plane architectures are implemented using the same code distance. However, a larger code distance reduces the logical error rate but increases resources. In fact, distance-5 code uses more resources but offers higher resilience to logical errors compared to distance-3 code. We propose a qubit-plane architecture for rotated and unrotated surface codes called Qentaurus that combines various code distances of logical qubits for robust error correction while maintaining qubit efficiency. Qentaurus is designed to be highly scalable regarding computation, layout, and code distance. We performed a case study using Qentaurus with distance-3 and -7 codes to evaluate the performance. Moreover, we additionally developed a qubit placement scheme that considers the critical path of the quantum circuit to reduce the logical error rate and gate count. Our main experimental results demonstrated that Qentaurus considerably reduces the overall logical error rate (by 15.76% on average and up to 25.25%) than that of the Distance-3 Checkerboard architecture. After additionally implementing the qubit placement scheme, the average reduction increases to 13.44% (up to 39.07%). Notably, the Qentaurus-37 maintains logical error rates comparable to those of the Distance-5 Checkerboard, achieving considerable qubit efficiency. The Distance-5 Checkerboard demands 227.7% more physical qubits than that required by the Distance-3 Checkerboard, while Qentaurus-37 utilizes just 131.2% of the physical qubits required by Distance-3 the Checkerboard, marking a substantial reduction of 96.5% in the resource gap. The overall gate count is reduced by an average of 1.74% with Qentaurus alone and by 3.33% on average with the qubit placement scheme. We believe that the proposed Qentaurus and qubit placement scheme have the potential to significantly improve the error-correction performance of large-scale quantum computers in practical applications.
Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.