Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.
Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.
Abstract Fault-tolerant quantum computing requires many qubits with long lifetimes and accurate quantum gate operations. However, external noise limits the computing time and hampers accurate quantum gate operations. Quantum error correction (QEC) codes may extend such limits, but imperfect gate operations during QEC cause errors, which could cancel out QEC. We used density matrix simulations to examine the performance of QEC codes with five qubits. In current quantum devices, less than ten qubits are needed to conduct sufficient gate operations within their lifetime so that it is feasible to implement QEC codes. We analyzed the maximum tolerable error rate and error correction effect of individual QEC codes according to the qubit arrangement and gate accuracy. Assuming a 0.1% gate error probability, a logical ∣ 1 〉 state encoded by a five-qubit QEC code is expected to have a 0.25 higher fidelity than its physical counterpart.
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while operating the logical qubit, and are essential for realizing error suppression in practice. While fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. In this work, we experimentally demonstrate fault-tolerant preparation, measurement, rotation, and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6% and a Clifford gate error of 0.3% after error correction. Additionally, we prepare magic states with fidelities exceeding the distillation threshold, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant operation. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.
Quantum computers hold the promise to solve some hard problems that are intractable for even the most powerful current supercomputers. One of the most famous examples is Shor's algorithm for factorizing large numbers, which has exponential speedup compared to its best classical counterparts. However, running such an algorithm will require to build a large-scale quantum computer consisting of thousands or even millions of qubits that include quantum error correction (QEC) and fault-tolerant (FT) mechanisms. Quantum computing is already a reality with the so-called Noisy Intermediate-Scale Quantum (NISQ) processors, some of them available in the cloud. Noisy refers to the imperfect control over the qubits and intermediate-scale to the relatively low number of quits (from fifty to a few hundred). Although current and near-term quantum devices will not have enough qubits for implementing large and fully corrected quantum computations, the use of small quantum error correction codes may extend the computation lifetime of NISQ devices. In this context and as a first step, it is important to test and demonstrate the fault-tolerance of these QEC codes. In this thesis, we explore the fault-tolerance of two small quantum correction codes that are good candidates to be applied to NISQ processors, the [[4,2,2]] code and the [[7,1,3]] Steane code. To this purpose, by following the FT criterion prosed by Daniel Gottesman in 2016, we tested both codes using two simulators, the stabilizer formalism simulator that includes quite simple error models and a full density matrix simulator called quantumsim, which includes more realistic noise. The simulations are performed under reasonable noise parameter values. For the [[4,2,2]] code, 235 circuits are tested based on the two simulators. The results show that in the stabilizer formalism simulation, the FT criterion is satised for all circuits, while not fully satisfied in the full density matrix simulation. For the [[7,1,3]] Steane code, we use a parallel-flag error correction implementation which is tested using the full density matrix simulator. Our results show that without applying any QEC cycle, for all circuits (84 circuits for 1 logical qubit simulation and 452 circuits for 2 logical qubits simulation), the error rate of the encoded circuits is lower than the unencoded ones. Adding a quantum error correction (QEC) cycle will in general increase the error rate of the computation.
Surface-code quantum error correction (QEC) is pivotal for fault-tolerant quantum computing, but its energy efficiency remains underexplored. This work derives a practical lower bound on the energy cost per logical-qubit operation, accounting for gate-fidelity decay's impact on code distance and physical-qubit overhead. By modeling the energy consumption of gate operations and error correction, we express the total cost as $ E = (E_g N_g + E_c N_c)/N_l $, where $ E_g $, $ E_c $, $ N_g $, $ N_c $, and $ N_l $ represent gate and physical-qubit energy costs, gate counts, physical-qubit counts, and logical qubit counts, respectively. Gate-fidelity decay increases the required code distance $ d $, scaling $ N_c $ and thus $ E $. We propose normalizing computational cost in joules per logical-qubit operation (JPCUB), isolating logical work from error-correction overhead. Quantitative predictions for $ E_g $, $ E_c $, and $ N_c $ remain [to verify], but the functional dependence on $ d $ and gate fidelities is established. This framework informs energy-efficient QEC design and benchmarks. ## 1. Introduction Surface codes enable fault-tolerant quantum computation by encoding logical qubits in a 2D lattice of physical qubits, correcting errors through syndrome measurements. However, the energy cost per logical operation—critical for scalability—remains poorly quantified. While theoretical foundations exist (Raussendorf & Terhal, 2006; Kitaev, 2003), prior work focuses on error-correction thresholds rather than energy efficiency. Here, we address this gap by deriving a lower bound on energy cost, considering how gate-fidelity decay necessitates larger code distances $ d $, increasing physical-qubit overhead $ N_c $. This analysis connects to the joules-per-compute (JPCUB) benchmark, advocating for energy normalization per logical qubit to disentangle computational work from error-correction costs. ## 2. Background Surface codes encode logical qubits using a 2D grid of
Quantum error correcting codes protect quantum computation from errors caused by decoherence and other noise. Here we study the problem of designing logical operations for quantum error correcting codes. We present an automated procedure that generates logical operations given known encoding and correcting procedures. Our technique is to use variational circuits for learning both the logical gates and the physical operations implementing them. This procedure can be implemented on near-term quantum computers via quantum process tomography. It enables automatic discovery of logical gates from analytically designed error correcting codes and can be extended to error correcting codes found by numerical optimization. We test the procedure by simulating small quantum codes of four to fifteen qubits showing that our procedure finds most logical gates known in the current literature. Additionally, it generates logical gates not found in the current literature for the [[5,1,2]] code, the [[6,3,2]] code, the [[8,3,2]] code, and the [[10,1,2]] code.