One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Quantum computers promise to solve computational problems that are inaccessible to classical machines. The reliable execution of large-scale quantum algorithms requires robust operations in the presence of noise. Quantum error correction addresses this challenge by encoding quantum information redundantly across several physical qubits, such that errors can be detected and corrected during a computation. However, no single error-correcting code intrinsically supports an inherently robust, fault-tolerant implementation of all gates needed for universal quantum computing. Moreover, most modern approaches to both quantum error correction and the implementation of universal logical operations on encoded qubits rely on mid-circuit measurements and feed-forward control. These types of operations are technologically demanding, often slow, and prone to high error rates, and they limit the overall success probability of quantum algorithms. In this thesis, we develop fault-tolerant protocols and circuits for quantum error correction and universal logical computation, with an emphasis on implementations compatible with current hardware systems. We first focus on fault-tolerant quantum error correction on small codes. By comparing different protocols, we identify trade-offs between compact circuit constructions and their robustness to noise. We then assess their practical performance by comparing numerical simulations of noisy circuits with experimental data. Beyond the preservation of encoded information, we study how universal logic can be implemented in a fault-tolerant manner on encoded qubits. A central approach considered in this thesis is code switching, in which logical information is transferred between two distinct error-correcting codes that support complementary sets of inherently fault-tolerant logical gates. In combination, these codes give access to a complete universal fault-tolerant logical gate set. In this thesis, we determine conditions that allow us to construct fault-tolerant protocols for code switching. We adapt these protocols to the capabilities of current hardware, thereby enabling the first experimental realization of universal fault-tolerant logic by means of code switching. However, the overall performance of these schemes is limited by slow and noisy mid-circuit measurements. To address this bottleneck, we construct a suite of measurement-free fault-tolerant universal operations that do not require any measurements during the execution of an algorithm. In this framework, error correction and logical operations are implemented coherently as part of the quantum circuit, without mid-circuit measurements or in-sequence classical control. We introduce measurement-free code-switching schemes that can be scaled to arbitrary code distances through concatenation, and which thereby provide, in principle, arbitrarily strong error suppression. We further tailor our approach to the capabilities of current trapped-ion quantum processors. New circuit constructions support the first experimental implementation of a logical quantum algorithm without mid-circuit measurements, demonstrated through Grover's search on three encoded qubits. Together, the results of this thesis expand the toolbox for early fault-tolerant quantum computation. They show how protocols for quantum error correction and universal logical gates can be designed without mid-circuit measurements with realistic hardware constraints in mind, opening new pathways towards universal quantum logic.
Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.
Quantum computing has the potential to transform information technology by offering algorithms for certain tasks, such as quantum simulation, that are vastly more efficient than what is possible with any classical device. But experimentally implementing practical quantum information processing is a very difficult task. Here we study two important, and closely related, aspects of this challenge: architectures for quantum computing, and quantum error correction Exquisite quantum control has now been achieved in small ion traps, in nitrogen-vacancy centres and in superconducting qubit clusters, but the challenge remains of how to scale these systems to build practical quantum devices. In Part I of this thesis we analyse one approach to building a scalable quantum computer by networking together many simple processor cells, thus avoiding the need to create a single complex structure. The difficulty is that realistic quantum links are very error prone. Here we describe a method by which even these error-prone cells can perform quantum error correction. Groups of cells generate and purify shared resource states, which then enable stabilization of topologically encoded data. Given a realistically noisy network (10% error rate) we find that our protocol can succeed provided that all intra-cell error rates are below 0.8%. Furthermore, we show that with some adjustments, the protocols we employ can be made robust also against high levels of loss in the network interconnects. We go on to analyse the potential running speed of such a device. Using levels of fidelity that are either already achievable in experimental systems, or will be in the near-future, we find that employing a surface code approach in a highly noisy and lossy network architecture can result in kilohertz computer clock speeds. In Part II we consider the question of quantum error correction beyond the surface code. We consider several families of topological codes, and determine the minimum requirements to demonstrate proof-of-principle error suppression in each type of code. A particularly promising code is the gauge color code, which admits a universal transversal gate set. Furthermore, a recent result of Bombin shows the gauge color code supports an error-correction protocol that achieves tolerance to noisy measurements without the need for repeated measurements, so called single-shot error correction. Here, we demonstrate the promise of single-shot error correction by designing a decoder and investigating its performance. We simulate fault-tolerant error correction with the gauge color code, and estimate a sustainable error rate, i.e. the threshold for the long time limit, of ~0.31% for a phenomenological noise model using a simple decoding algorithm.
Quantum error correction protects fragile quantum information by encoding it into a larger quantum system. These extra degrees of freedom enable the detection and correction of errors, but also increase the operational complexity of the encoded logical qubit. Fault-tolerant circuits contain the spread of errors while operating the logical qubit, and are essential for realizing error suppression in practice. While fault-tolerant design works in principle, it has not previously been demonstrated in an error-corrected physical system with native noise characteristics. In this work, we experimentally demonstrate fault-tolerant preparation, measurement, rotation, and stabilizer measurement of a Bacon-Shor logical qubit using 13 trapped ion qubits. When we compare these fault-tolerant protocols to non-fault tolerant protocols, we see significant reductions in the error rates of the logical primitives in the presence of noise. The result of fault-tolerant design is an average state preparation and measurement error of 0.6% and a Clifford gate error of 0.3% after error correction. Additionally, we prepare magic states with fidelities exceeding the distillation threshold, demonstrating all of the key single-qubit ingredients required for universal fault-tolerant operation. These results demonstrate that fault-tolerant circuits enable highly accurate logical primitives in current quantum systems. With improved two-qubit gates and the use of intermediate measurements, a stabilized logical qubit can be achieved.
Abstract Coherence times for superconducting qubits have greatly improved over time. Moreover, small logical qubit architectures using engineered dissipation have shown great promise for further improvements in the coherence of a logical qubit manifold comprised of few physical qubits. Nevertheless, optimal working parameters for small logical qubits are generally not well understood. This work presents several approaches to finding preferential parameter configurations by looking at three different cases of increasing complexity. We begin by looking at state stabilization of a single qubit using dissipation via coupling to a lossy object. We look at the limiting factors in this approach to error correction, and how we address those by numerically optimizing the parametric coupling strength with the lossy object having an effective time-varying dissipation rate—we call this a pulse-reset cycle. We then translate this approach to more efficient state stabilization to an abstracted three-qubit flip code, and end by looking at the very small logical qubit (VSLQ). By using these techniques, we can further increase logical state lifetimes for different architectures. We show significant advantages in using a pulse-reset cycle over numerically optimized, fixed parameter spaces.
Stabilized cat qubits that possess biased noise channel with bit-flip errors exponentially smaller than phase-flip errors. Together with a set of bias-preserving (BP) gates, cat qubits are a promising candidate for realizing hardware efficient quantum error correction and fault-tolerant quantum computing. Compared to dissipatively stabilized cat qubits, the Kerr cat qubits can in principle support faster gate operations with higher gate fidelity, benefiting from the large energy gap that protects the code space. However, the leakage of the Kerr cats can increase the minor type of errors and compromise the noise bias. Both the fast implementation of gates and the interaction with environment can lead to such detrimental leakage if no sophisticated controls are applied. In this work, we introduce new fine-control techniques to overcome the above obstacles for Kerr cat qubits. To suppress the gate leakage, we use the derivative-based transition suppression technique to design derivative-based controls for the Kerr BP gates. We show that the fine-controlled gates can simultaneously have high gate fidelity and high noise bias and when applied to concatenated quantum error correction, can not only improve the logical error rate but also reduce resource overhead. To suppress the environment-induced leakage, we introduce colored single-photon dissipation, which can continuously cool the Kerr cats and suppress the minor errors while not enhancing the major errors.