One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016)PRLTAO0031-900710.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

arXiv:1703.09762Physical Review LettersFeb 1, 201837 citations

Error-corrected gates on an encoded qubit

Philip Reinhold, Serge Rosenblum, Wen-Long Ma +3 more

arXiv:1907.12327Nature PhysicsJun 8, 202098 citations

Density-Matrix Simulation of Logical Qubit using 3-qubit Quantum Error Correction Code

Chungheon Baek, Tomohiro Ostuka, Seigo Tarucha +1 more

Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.Fault-tolerant quantum computing demands many qubits with long lifetimes to conduct accurate quantum gate operations. However, external noise limits the computing time of physical qubits. Quantum error correction codes may extend such limits, but imperfect gate operations introduce errors to the correction procedure as well. The additional gate operations required due to the physical layout of qubits exacerbate the situation. Here, we use density-matrix simulations to investigate the performance change of logical qubits according to quantum error correction codes and qubit layouts and the expected performance of logical qubits with gate operation time and gate error rates. Considering current qubit technology, the small quantum error correction codes are chosen. Assuming 0.1% gate error probability, a logical qubit encoded by a 5-qubit quantum error correction code is expected to have a fidelity 0.25 higher than its physical counterpart.

arXiv:1810.01029Oct 2, 20180 citations

Recursive Clifford noise reduction

Aharon Brodutch, Gregory Baimetov, Edwin Tham +1 more

Clifford noise reduction (CliNR) is a partial error correction scheme that reduces the logical error rate of Clifford circuits at the cost of a modest qubit and gate overhead. The CliNR implementation of an $n$ -qubit Clifford circuit of size $s$ achieves a vanishing logical error rate if $snp^2\rightarrow 0$ where $p$ is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When $np \rightarrow 0$ , the logical error rate can be vanishingly small. This implementation requires $\left(2\left\lceil \log(sp)\right\rceil+3\right)n+1$ qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.Clifford noise reduction (CliNR) is a partial error correction scheme that reduces the logical error rate of Clifford circuits at the cost of a modest qubit and gate overhead. The CliNR implementation of an $n$-qubit Clifford circuit of size $s$ achieves a vanishing logical error rate if $snp^2\rightarrow 0$ where $p$ is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When $np \rightarrow 0$, the logical error rate can be vanishingly small. This implementation requires $\left(2\left\lceil \log(sp)\right\rceil+3\right)n+1$ qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.

quant-pharXiv:2511.22624Nov 28, 20250 citations

n

-qubit Clifford circuit of size

s

achieves a vanishing logical error rate if

snp^2\rightarrow 0

where

p

is the physical error rate. Here, we propose a recursive version of CliNR that can reduce errors on larger circuits with a relatively small gate overhead. When

np \rightarrow 0

, the logical error rate can be vanishingly small. This implementation requires

\left(2\left\lceil \log(sp)\right\rceil+3\right)n+1

qubits and at most $24 s \left\lceil(sp)^4\right\rceil $ gates. Using numerical simulations, we show that the recursive method can offer an advantage in a realistic near-term parameter regime. When circuit sizes are large enough, recursive CliNR can reach a lower logical error rate than the original CliNR with the same gate overhead. The results offer promise for reducing logical errors in large Clifford circuits with relatively small overheads.