Superconductor electronics is gaining traction as the increasing density of integration of recent and future digital circuits pushes the limits of available simulation models. Designers often make assumptions in the behavioral models of circuit elements when simulating circuits. For instance high-frequency effects have been neglected so far in the design of superconductor digital circuits, while much has been done in the past to model them. Indeed these effects had little influence on the accuracy of digital circuits simulations until recently. The increase in clock frequency, combined with longer paths between cells and higher yield requirements for large scale circuits fabrication, has led to the need of more accurate models, including in particular high frequency effects such as quasi-particle losses. To do so, this work uses a state-space model that describes the circuit under study with internal state variables and a set of first-order differential equations. We extract the state-space model while analytically enforcing the DC requirements of superconductors that are required to account for flux-trapping. The model accurately traps flux at DC, and given the model is fitted with enough poles, the high-frequency effects are also accurate relative to the reference model. The high-frequency effects have been investigated on a practical circuit: a long-distance Passive Transmission Line (PTL) designed for the high-density MIT Lincoln Labs SFQ5ee process. Results obtained in the time domain allow to observe the effects of dispersion of pulses traveling on long paths of PTLs. Indeed the energy of voltage pulses is sufficient to break Cooper pairs for the highest clock frequencies.
Superconductor electronics is gaining traction as the increasing density of integration of recent and future digital circuits pushes the limits of available simulation models. Designers often make assumptions in the behavioral models of circuit elements when simulating circuits. For instance high-frequency effects have been neglected so far in the design of superconductor digital circuits, while much has been done in the past to model them. Indeed these effects had little influence on the accuracy of digital circuits simulations until recently. The increase in clock frequency, combined with longer paths between cells and higher yield requirements for large scale circuits fabrication, has led to the need of more accurate models, including in particular high frequency effects such as quasi-particle losses. To do so, this work uses a state-space model that describes the circuit under study with internal state variables and a set of first-order differential equations. We extract the state-space model while analytically enforcing the DC requirements of superconductors that are required to account for flux-trapping. The model accurately traps flux at DC, and given the model is fitted with enough poles, the high-frequency effects are also accurate relative to the reference model. The high-frequency effects have been investigated on a practical circuit: a long-distance Passive Transmission Line (PTL) designed for the high-density MIT Lincoln Labs SFQ5ee process. Results obtained in the time domain allow to observe the effects of dispersion of pulses traveling on long paths of PTLs. Indeed the energy of voltage pulses is sufficient to break Cooper pairs for the highest clock frequencies.
ENGLISH ABSTRACT: In this thesis, we cover various methods that improve high-frequency Single Flux Quantum electronics design. Accurately modelling high-frequency effects is vital in high-frequency Single Flux Quantum electronics design. The passive transmission line is, currently, the most inaccurately modelled circuit component. We, therefore, developed a new 2D quasiTransverse-Magnetic method to calculate transmission line properties of superconductor structures. The new method can take into account quasi-particle losses as well as dielectric losses. The frequency response of a passive transmission line with arbitrary length can then readily be obtained from the transmission line properties. The high-frequency response is informative, but a time-domain simulation model is necessary to determine the effect on high-frequency circuit dynamics. Accordingly, we developed the Superconductor Vector Fitting algorithm so that we can take arbitrary superconductor frequency responses and convert them into time-domain simulation models. Complex dynamical behaviour, made more complicated by the new numerical simulation models, currently prohibits designing circuits by only using design equations. Automatic optimization routines are used to adjust circuit parameters to improve fabrication yield. Existing routines suffer from issues ranging from suboptimal circuits to severe performance issues. We developed a new and novel yield optimization algorithm, Distance-To-Failure-Maximization, that can be used to optimize superconductor circuits that are verified u sing time-domain simulations. High-frequency circuits can be sensitive to changes in bias current from parasitics mutual inductances. We developed the fundamental inductance model to model all inductive effects accurately. The fundamental inductance model can also be used to construct design equations which accounts for parasitic effects as well as reduce the number of unknowns in the yield optimization procedure. We use all the above methods in a detailed case study on the design of a JTLT. We take into account attenuation, impedance mismatch, flux mismatch, and resonance during the design of the JTLT circuit. With this, we conclude that the methods we developed have brought significant improvements to high-frequency Single Flux Quantum design.
Superconducting technologies are moving toward very large-scale integration (VLSI) of circuits. Passive transmission lines (PTLs) are used to quickly and efficiently propagate single flux quantum pulses between separated logic elements of these VLSI circuits. PTLs are often insufficiently modeled to correspond to reality. Therefore, the PTL needs to be thoroughly studied to determine realistic propagation characteristics. A quasi-transverse magnetic (TM) formulation is used to study superconducting passive transmission lines. The ambient temperature and changes in penetration depth with frequency are taken into account when solving the electromagnetic fields of a PTL. Per-frequency transmission line parameters are extracted from the quasi-TM field solutions. The results show a very close correlation to TetraHenry, an existing 3D solver, at significantly reduced computational cost. The results also clearly show that PTL propagation characteristics are sensitive to frequency and temperature.
Abstract Interconnects are a major discriminator for superconducting digital technology, enabling energy-efficient data transfer and high-bandwidth heterogeneous integration. We report a method to simulate propagation of picosecond pulses in superconducting passive transmission lines (PTLs). A frequency-domain propagator model obtained from the Ansys high-frequency structure simulator (HFSS) field solver is incorporated in a Cadence Spectre circuit model, so that the particular PTL geometry can be simulated in the time-domain. The Mattis Bardeen complex conductivity of the superconductor is encoded in the HFSS field solver as a complex-conductivity insulator. Experimental and simulation results show that Nb 20 Ω microstrip PTLs with 200 nm interlayer dielectric thickness can support propagation of a single-flux-quantum pulse up to 7 mm and a double-flux-quantum pulse up to 28 mm.
Superconductive electronics based on Josephson junctions (JJ) is a promising cryogenic alternative technology to complementary metal oxide semiconductor (CMOS) technology for ultra-low energy, high speed stationary applications. For complex superconductive systems, the automated routing process determines the topology and methodology to connect cells while satisfying design constraints. On-chip signal routing has become an issue of growing importance in modern superconductive technologies; particularly, single flux quantum (SFQ) systems. Specialized routing methods for these systems are required. These routing methods include passive transmission lines (PTLs) and Josephson transmission lines (JTLs) behaving as interconnects. A primary issue within a long SFQ interconnect is the effects of resonance due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology to reduce and manage these resonance effects is required for driving long and short interconnect in VLSI complexity SFQ systems. Permissible interconnect lengths are suggested to ensure the reflections do not affect the returning signals. The microwave behavior of the interconnect striplines is also considered to accurately estimate the surface inductance of the lines. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is discussed. Another primary issue within SFQ circuits is coupling noise between transmission striplines, degrading performance and decreasing margins. Inductive and capacitive coupling noise between the routing layers, for the MIT LL SFQ5ee process, is described. An analysis of inductive and capacitive coupling noise can determine the minimum physical spacing between lines to enhance the automated routing process in large scale systems. The increasing complexity of modern SFQ circuits has also made the issue of flux trapping of growing importance. The use of wide striplines for signal routing has exacerbated this issue. Trapped residual magnetic fields within the striplines damage the operability of superconductive circuits. Area efficient topologies for striplines are introduced to manage flux trapping in large scale SFQ circuits. These topologies are composed of several narrow lines rather than a single wide stripline. The first approach is a narrow parallel line topology in series with small resistors where each narrow line is connected to a single small resistor and via. The resistors in the parallel line topology remove any trapped fluxons and break any loops while requiring additional vias. The second topology is a fingered narrow line topology. The fingered narrow line topology enhances the scalability of SFQ systems while not requiring additional area and vias. These proposed topologies require significantly less area while preventing flux from being trapped within wide superconductive striplines and reducing coupling noise between striplines. These methodologies and techniques are intended as guidelines to enable robust routing with superconductive interconnects. With these and other advances in design methodologies for superconductive electronics, the complexity of SFQ circuits is expected to greatly increase.
As the complexity of superconductor circuits grows, we envision a dense network of passive transmission lines (PTLs) being used to interconnect cells in rapid-single-flux-quantum (RSFQ) circuits. In our library approach, each cell has dedicated tracks as place holders for routing PTLs. Higher impedance PTLs are desirable due to their narrower width. However, at higher impedance, the margins for the PTL receiver degrade rapidly. We have designed, fabricated, tested, and simulated passive transmission lines (PTLs) for high-speed interconnects in the MIT-LL SFQ5ee 10 kA/cm2process. For the symmetric dual ground planes case, PTLs are in the M1 layer with M0 and M2 ground planes, or in the M3 layer with M2 and M4 ground planes. For the asymmetrical dual ground planes case, PTLs are in M2 or M3 layers with M1 and M4 ground planes. We report ±30% margins for these PTLs. We investigate the receiver margins for these PTLs and report impact of margins as a function of corners, interlayer transitions, variants of drivers, and receivers. We demonstrate 100 GHz PTL operation in ring oscillator measurements. We have also adopted multi-layer multi-conductor transmission line models for PTL simulation. We observe good model-to-hardware correlation for low- and high-frequency operation.
A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm × 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional ‘dummy’ GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ∼ 1.2 µT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-µm-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance,${{{\boldsymbol{t}}}_{\boldsymbol{c}}} \approx $0.6 µm, between them. The presence of two or more GPs spaced below thetcrendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).