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Methods that improve high frequency Single Flux Quantum electronics design

Paul le Roux

Published Mar 1, 2021• 0 citations
OpenAlex

Abstract

ENGLISH ABSTRACT: In this thesis, we cover various methods that improve high-frequency Single Flux Quantum electronics design. Accurately modelling high-frequency effects is vital in high-frequency Single Flux Quantum electronics design. The passive transmission line is, currently, the most inaccurately modelled circuit component. We, therefore, developed a new 2D quasiTransverse-Magnetic method to calculate transmission line properties of superconductor structures. The new method can take into account quasi-particle losses as well as dielectric losses. The frequency response of a passive transmission line with arbitrary length can then readily be obtained from the transmission line properties. The high-frequency response is informative, but a time-domain simulation model is necessary to determine the effect on high-frequency circuit dynamics. Accordingly, we developed the Superconductor Vector Fitting algorithm so that we can take arbitrary superconductor frequency responses and convert them into time-domain simulation models. Complex dynamical behaviour, made more complicated by the new numerical simulation models, currently prohibits designing circuits by only using design equations. Automatic optimization routines are used to adjust circuit parameters to improve fabrication yield. Existing routines suffer from issues ranging from suboptimal circuits to severe performance issues. We developed a new and novel yield optimization algorithm, Distance-To-Failure-Maximization, that can be used to optimize superconductor circuits that are verified u sing time-domain simulations. High-frequency circuits can be sensitive to changes in bias current from parasitics mutual inductances. We developed the fundamental inductance model to model all inductive effects accurately. The fundamental inductance model can also be used to construct design equations which accounts for parasitic effects as well as reduce the number of unknowns in the yield optimization procedure. We use all the above methods in a detailed case study on the design of a JTLT. We take into account attenuation, impedance mismatch, flux mismatch, and resonance during the design of the JTLT circuit. With this, we conclude that the methods we developed have brought significant improvements to high-frequency Single Flux Quantum design.

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ENGLISH ABSTRACT: In this thesis, we cover various methods that improve high-frequency Single Flux Quantum electronics design. Accurately modelling high-frequency effects is vital in high-frequency Single Flux Quantum electronics design. The passive transmission line is, currently, the most inaccurately modelled circuit component. We, therefore, developed a new 2D quasiTransverse-Magnetic method to calculate transmission line properties of superconductor structures. The new method can take into account quasi-particle losses as well as dielectric losses. The frequency response of a passive transmission line with arbitrary length can then readily be obtained from the transmission line properties. The high-frequency response is informative, but a time-domain simulation model is necessary to determine the effect on high-frequency circuit dynamics. Accordingly, we developed the Superconductor Vector Fitting algorithm so that we can take arbitrary superconductor frequency responses and convert them into time-domain simulation models. Complex dynamical behaviour, made more complicated by the new numerical simulation models, currently prohibits designing circuits by only using design equations. Automatic optimization routines are used to adjust circuit parameters to improve fabrication yield. Existing routines suffer from issues ranging from suboptimal circuits to severe performance issues. We developed a new and novel yield optimization algorithm, Distance-To-Failure-Maximization, that can be used to optimize superconductor circuits that are verified u sing time-domain simulations. High-frequency circuits can be sensitive to changes in bias current from parasitics mutual inductances. We developed the fundamental inductance model to model all inductive effects accurately. The fundamental inductance model can also be used to construct design equations which accounts for parasitic effects as well as reduce the number of unknowns in the yield optimization procedure. We use all the above methods in a detailed case study on the design of a JTLT. We take into account attenuation, impedance mismatch, flux mismatch, and resonance during the design of the JTLT circuit. With this, we conclude that the methods we developed have brought significant improvements to high-frequency Single Flux Quantum design.
Superconductor electronics is gaining traction as the increasing density of integration of recent and future digital circuits pushes the limits of available simulation models. Designers often make assumptions in the behavioral models of circuit elements when simulating circuits. For instance high-frequency effects have been neglected so far in the design of superconductor digital circuits, while much has been done in the past to model them. Indeed these effects had little influence on the accuracy of digital circuits simulations until recently. The increase in clock frequency, combined with longer paths between cells and higher yield requirements for large scale circuits fabrication, has led to the need of more accurate models, including in particular high frequency effects such as quasi-particle losses. To do so, this work uses a state-space model that describes the circuit under study with internal state variables and a set of first-order differential equations. We extract the state-space model while analytically enforcing the DC requirements of superconductors that are required to account for flux-trapping. The model accurately traps flux at DC, and given the model is fitted with enough poles, the high-frequency effects are also accurate relative to the reference model. The high-frequency effects have been investigated on a practical circuit: a long-distance Passive Transmission Line (PTL) designed for the high-density MIT Lincoln Labs SFQ5ee process. Results obtained in the time domain allow to observe the effects of dispersion of pulses traveling on long paths of PTLs. Indeed the energy of voltage pulses is sufficient to break Cooper pairs for the highest clock frequencies.
ENGLISH ABSTRACT: Rapid Single Flux Quantum (RSFQ) cells are key in the design of complex and applicable RSFQ electronic circuits. These cells are low-level circuit elements that are used repeatedly to build larger, applicable RSFQ circuitry. Making these cells simple to layout and manufacture, but reliable for extensive use demands a careful development process for RSFQ cells. Cell functionality is verified through simulations, thereafter the cell is laid out in special software packages. Inductance of on-chip superconductor structures is extracted through careful modelling with numerical field solver software. A cell library has been developed by incorporating existing or published cells after further analysis and optimization, as well as developing new cells. Cells that have been adapted into the library include the Josephson transmission line (JTL), Splitter, Merger, D-Flip Flop (DFF), T-Flip Flop (TFF), NOT, AND, OR and XOR, DC-SFQ and SFQ-DC and PTL Driver and Receivers. New cells include NOR, NAND and XNOR. The cells were designed for the IPHT’s RSFQ1D 1kA/cmª and Hypres’ 4.5kA/cmª processes. The cells in the library have good bias current operating margins obtained through simulations (> ±26%). All cells have all the parameters listed in the thesis including extracted inductance values. In order to have a complete and verified RSFQ cell library, cells have been sent for fabrication at IPHT and Hypres facilities. These cells can now be tested on-chip, in the laboratory, to establish functionality and practical bias current margins. All test signal patterns and bias currents required for testing are defined to allow co-workers or collaborators to test the cells.
Along with the improvement of integration and the requirement of high-speed operation, the passive transmission line (PTL) plays a significant role in superconducting integrated circuits due to its intrinsic advantage of extremely low propagation delay and low signal loss in long-distance transmission. Good impedance matching is critical to reduce the signal reflection in the transmission line and maximize the power transferred. Based on the PTL wiring layer selection under SIMIT-Nb03 process, we studied the equivalent input/output impedance for Josephson junction (JJ) at the IO port and explored a method of impedance matching in rapid-single-flux-quantum circuits by adjusting the Stewart McCumber parameterβC{\beta }_{\bm{C}}βC​of the JJ in the design of the PTL's driver and receiver. Furthermore, the accompanying influence from JJ's modifiedβC{\beta }_{\bm{C}}βC​on the performance of the driver and receiver is evaluated to maximize the profit of the functional circuits. The common-used serial resistor is removed to obtain a balanced bias margin for the PTL circuits. The proposed PTL has been designed and tested based on SIMIT-Nb03 fabrication process. In total,$ \pm $30% bias margin for the PTL is achieved at low frequency and high frequency (40 GHz) contrast tests, including operation speed and transmission length as test vector. Additionally, a frequency sweep for 1 mm PTL is performed by the designed ring oscillator on the chip. The maximum working frequency is up to 129 GHz, with a margin duration of 8%.
We developed a design approach for interface circuits to connect Single Flux Quantum (SFQ) cells by using passive transmission lines (PTL's). In the approach, an interface circuit between a PTL and JTL is optimized to obtain a standard interface circuit, and then, modifications are made to previously designed SFQ cells and the standard interface circuit to connect the SFQ cells by using PTL's. The key point is the use of approximately the same interface circuit with every SFQ cell to maintain the matching condition between the interface circuit and the PTL's. Based on this approach, we designed an interface circuit and a test circuit composed of two D-flip-flops connected using 2-mm-long PTL's via the interface circuits. The impedance of the PTL was 2 /spl Omega/. We achieved high-speed operation of the test circuit up to 35 GHz with a bias margin of -15/+30%.
Superconductive electronics based on Josephson junctions (JJ) is a promising cryogenic alternative technology to complementary metal oxide semiconductor (CMOS) technology for ultra-low energy, high speed stationary applications. For complex superconductive systems, the automated routing process determines the topology and methodology to connect cells while satisfying design constraints. On-chip signal routing has become an issue of growing importance in modern superconductive technologies; particularly, single flux quantum (SFQ) systems. Specialized routing methods for these systems are required. These routing methods include passive transmission lines (PTLs) and Josephson transmission lines (JTLs) behaving as interconnects. A primary issue within a long SFQ interconnect is the effects of resonance due to the imperfect match between the PTLs and Josephson junctions. A repeater insertion methodology to reduce and manage these resonance effects is required for driving long and short interconnect in VLSI complexity SFQ systems. Permissible interconnect lengths are suggested to ensure the reflections do not affect the returning signals. The microwave behavior of the interconnect striplines is also considered to accurately estimate the surface inductance of the lines. A closed-form expression describing the dependence of the surface inductance of a stripline on the line thickness, magnetic field, and current density is discussed. Another primary issue within SFQ circuits is coupling noise between transmission striplines, degrading performance and decreasing margins. Inductive and capacitive coupling noise between the routing layers, for the MIT LL SFQ5ee process, is described. An analysis of inductive and capacitive coupling noise can determine the minimum physical spacing between lines to enhance the automated routing process in large scale systems. The increasing complexity of modern SFQ circuits has also made the issue of flux trapping of growing importance. The use of wide striplines for signal routing has exacerbated this issue. Trapped residual magnetic fields within the striplines damage the operability of superconductive circuits. Area efficient topologies for striplines are introduced to manage flux trapping in large scale SFQ circuits. These topologies are composed of several narrow lines rather than a single wide stripline. The first approach is a narrow parallel line topology in series with small resistors where each narrow line is connected to a single small resistor and via. The resistors in the parallel line topology remove any trapped fluxons and break any loops while requiring additional vias. The second topology is a fingered narrow line topology. The fingered narrow line topology enhances the scalability of SFQ systems while not requiring additional area and vias. These proposed topologies require significantly less area while preventing flux from being trapped within wide superconductive striplines and reducing coupling noise between striplines. These methodologies and techniques are intended as guidelines to enable robust routing with superconductive interconnects. With these and other advances in design methodologies for superconductive electronics, the complexity of SFQ circuits is expected to greatly increase.
To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 4 x 4 switch having block-to-block passive interconnections and a 2 x 2 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFO circuits having passive interconnections.