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Beijing Hangkong Hangtian Daxue xuebao

Design and implementation of multi-rate quasi-cyclic low-density parity-check code decoder

Ling Zhao, Xiaolin Zhang, Zhi Gang

Published Apr 30, 2008• 1 citation
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Low-density parity-check (LDPC) codes are one of the most effective error controlling methods, which now are widely used in multiple communication systems, for example, DVB-S2, 802.16e, etc. In these communication standards, the adopted LDPC codes are all quasi-cyclic low-density parity-check (QC-LDPC) codes. The parity-check matrices of QC-LDPC codes consist of arrays of circulants, in which each row is the cyclic shift of the row above it, and the first row is the cyclic shift of the last row. This character of QC-LDPC codes results in the linear encoding complexity and opens the door for the multi-mode LDPC decoders with enough flexibility of resource multiplexing. Based on the quasi-cyclic character of QC-LDPC codes, a design method for multi-mode QC-LDPC decoders is proposed in this paper. The node memory is skillfully organized and can be expediently addressed by a simple control unit to save memory consumption in hardware implementation. Then this design method is implemented and test on Field Programmable Gate Array (FPGA) platform. The test results show that the resource occupied by the multi-mode decoder is only a little more than that of maximal resource occupied by the single-mode decoder, and this multi-mode decoder can support at least 3 code rates with the throughput higher than 100 Mbps when the iteration number is fixed to 12 and the clock frequency is set to 200 MHZ.

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An Expurgating-Based Method for Constructing Multi-Rate Non-Binary Quasi-Cyclic LDPC Codes

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This letter presents a new method for constructing the multi-rate non-binary quasi-cyclic low-density parity-check codes by expurgating a high-rate mother code. A matrix-theoretic approach is applied to design the parity-check matrices of the proposed codes. The resulting codes possess a quasi-cyclic structure, which is desirable for hardware implementations of the encoder and decoder. The codes can also be encoded directly with parity-check matrices due to the block dual-diagonal structure. Simulation results show that the codes can achieve good performance within a wide range of code rates both in the waterfall region and in the error-floor region.

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Quasi-Cyclic Generalized LDPC Codes With Low Error Floors

Gianluigi Liva, W.E. Ryan, Marco Chiani

In this paper, a novel methodology for designing structured generalized low-density parity-check (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call low-density parity-check (LDPC) code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.

IEEE Transactions on Communications•Dec 1, 2007•9 citations
Low-density parity-check (LDPC) codes are one of the most effective error controlling methods, which now are widely used in multiple communication systems, for example, DVB-S2, 802.16e, etc. In these communication standards, the adopted LDPC codes are all quasi-cyclic low-density parity-check (QC-LDPC) codes. The parity-check matrices of QC-LDPC codes consist of arrays of circulants, in which each row is the cyclic shift of the row above it, and the first row is the cyclic shift of the last row. This character of QC-LDPC codes results in the linear encoding complexity and opens the door for the multi-mode LDPC decoders with enough flexibility of resource multiplexing. Based on the quasi-cyclic character of QC-LDPC codes, a design method for multi-mode QC-LDPC decoders is proposed in this paper. The node memory is skillfully organized and can be expediently addressed by a simple control unit to save memory consumption in hardware implementation. Then this design method is implemented and test on Field Programmable Gate Array (FPGA) platform. The test results show that the resource occupied by the multi-mode decoder is only a little more than that of maximal resource occupied by the single-mode decoder, and this multi-mode decoder can support at least 3 code rates with the throughput higher than 100 Mbps when the iteration number is fixed to 12 and the clock frequency is set to 200 MHZ.
This letter presents a new method for constructing the multi-rate non-binary quasi-cyclic low-density parity-check codes by expurgating a high-rate mother code. A matrix-theoretic approach is applied to design the parity-check matrices of the proposed codes. The resulting codes possess a quasi-cyclic structure, which is desirable for hardware implementations of the encoder and decoder. The codes can also be encoded directly with parity-check matrices due to the block dual-diagonal structure. Simulation results show that the codes can achieve good performance within a wide range of code rates both in the waterfall region and in the error-floor region.
In this paper, a novel methodology for designing structured generalized low-density parity-check (G-LDPC) codes is presented. The proposed design results in quasi-cyclic G-LDPC codes for which efficient encoding is feasible through shift-register-based circuits. The structure imposed on the bipartite graphs, together with the choice of simple component codes, leads to a class of codes suitable for fast iterative decoding. A pragmatic approach to the construction of G-LDPC codes is proposed. The approach is based on the substitution of check nodes in the protograph of a low-density parity-check code with stronger nodes based, for instance, on Hamming codes. Such a design approach, which we call low-density parity-check (LDPC) code doping, leads to low-rate quasi-cyclic G-LDPC codes with excellent performance in both the error floor and waterfall regions on the additive white Gaussian noise channel.